Maxim Integrated MAXQ7666 - Manual (Page 154)

MAXQ7665/MAXQ7666 User’s Guide
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processor has removed itself from the BUSOFF condition, it also clears BSS = 0, sets SWINT = 1, and clears both the transmit- and
receive-error counters to 00h.
The following two situations are examples of how the autobaud function works on the CAN processor. In the first case, consider three
nodes, A, B and C, with nodes A and B operating in the normal CAN operational mode (nonautobaud) and node C (a MAXQ7665/
MAXQ7666 CAN processor) is attempting to establish a proper baud rate using the autobaud features. If node A transmits a message,
node B acknowledges this message, and node C also receives the acknowledged message if it has the same baud rate. If node C
does not have the same baud rate as nodes A and B, node C detects the mismatch via the respective error count. Node C then pro-
ceeds to adapt its baud rate and attempt to receive the following message.
In the second case, consider a system with only two nodes on the CAN bus. Consider node A in the autobaud mode and the second
node on the bus in the normal CAN operational mode. Node B transmits a message and does not receive an acknowledgment, since
there is no third node on the bus that is also properly synchronized with the bus and in the normal CAN operational mode. Once node
B enters into an error-passive mode (after 16 repeated messages), it begins to send passive error flags. Note that when node B is oper-
ating in an error-passive mode, it does not send any dominant errors flags to the bus. Once node A has established the proper baud
rate, it receives the correct message. The internal autobaud loopback path also allows the passive acknowledgment error sent by node
B to be ANDed with the dominant internally transmitted acknowledgment bit from node A. As such, node A sees no errors, which estab-
lishes the fact that it is properly synchronized with the bus. Node A now exits out of the autobaud mode (AUTOB = 0) and enters into
the normal CAN operational mode (with full transmit capability to the CAN bus). In this mode, node A then acknowledges the next mes-
sage from node B.
Bit 1: Error Count Select (ERCS). The ERCS bit establishes in which level the error counters set or clear the EX96/128 bit in the CAN
0 status register. When ERCS = 0, the EC96/128 flag operates in an EC96 mode. In this mode, the EC96/128 bit sets to 1 whenever
the error count of either the transmit- or receive-error counters reach a level of 96 or greater. When ERCS = 1, the EC96/128 flag oper-
ates in an EC128 mode. In the EC128 mode, the EC96/128 flag is set to 1 whenever the error count of either the transmit- or receive-
error counters reach a level of 128 or greater.
Bit 0: Software Initialization (SWINT). (Unrestricted read/write if BSS = 0 and read-only if BSS = 1.) The SWINT bit establishes the
initialization state for CAN 0, which disables CAN 0 Bus activity to allow the processor to modify the dual port CAN control/status/mask
registers assigned to the message centers without corrupting messages. When SWINT is set to 1 and after completion of the last recep-
tion, transmission, or after arbitration was lost or an error condition occurred, all CAN 0 bus activity is disabled, allowing the proces-
sor to initialize any or all of the CAN 0 dual port memory. Note that the term "after arbitration lost" denotes the fact the arbitration was
lost and the reception following this lost arbitration is completed. Recall that the CAN processor immediately becomes a receiver after
it has lost its arbitration on the CAN bus. A read of the SWINT bit verifies when the CAN processor software initialization mode has been
engaged or removed. Although the transmit- and receive-error counters are not cleared when the SWINT bit is set, the CAN 0 trans-
mit- and receive-error counters can be altered by software through the use of the CAN 0 transmit-error peripheral register, as long
SWINT = 1. Setting SWINT to 1 also clears the SIESTA bit independently of what is stored to the SIESTA bit location during or prior to
the write of the C0C register. Clearing SWINT = 0 also disables the microcontroller from writing to the first 16 bytes of the CAN dual
port memory. These 16 locations make up the CAN 0 control/status/mask registers. When SWINT = 0, the microcontroller is allowed to
write to any of the MOVX dual port message center register sites. All dual port registers are readable at any time, independent of the
SWINT bit. Also note that the SWINT bit does not alter the read or write access to any of the CAN 0 peripheral registers or dual port
CAN message center registers. SWINT is programmed to 0 when the processor has completed the dual port control/status/mask ini-
tialization and CAN 0 bus activity has started. Software write access to the error counters is disabled when SWINT is cleared to 0. A
BUSOFF condition is caused by a high number of errors on the CAN bus. When a BUSOFF condition occurs, the CAN processor clears
the SWINT bit to 0 and immediately starts a bus recover and power-up sequence. During this time, the microcontroller is limited to only
reading this bit. All microcontroller write access to SWINT is disabled when BSS = 1.
If the SWINT bit is set by a system reset, programming the CRST bit or setting the SWINT bit without the prior detection of a BUSOFF
condition can cause an adverse condition. Clearing SWINT by software allows the CAN processor to synchronize itself to the CAN bus
after the CAN processor executes a power-up sequence (11 recessive bits). The power-up sequence requires the CAN processor to
detect 11 consecutive recessive bits. (In CAN protocol, this is termed a power-up sequence.) When SWINT = 0 by a BUSOFF condi-
tion, BUSOFF forces the CAN processor to initiate a standard BUSOFF recovery sequence (128 x 11 recessive bits). This is followed
by entering into a reset state, requiring a power-up sequence (11 recessive bits), after which the CAN processor enters into the idle
state (normal operation, BSS = 0) and sets the SWINT bit to 1. This bit is not intended for use in changing data within the message
centers after the CAN processor is placed into operation. Changes to the arbitration or data fields in the message centers should be
done through the use of the MSRDY bit in the respective message (1–15) control registers. The SWINT bit is locked into the SWINT =
1 state until the bus timing registers are programmed to valid states. (The invalid states are 00h. See the CAN bus timing registers in
the CAN control/status/mask registers section.)
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