Maxim Integrated MAXQ7666 - Manual (Page 305)

11.2.8 System Control Register (SC)
Register Description: System Control Register
Register Name: SC
Register Address: Module 08h, Index 08h
Bit 7: Test Access (JTAG) Port Enable (TAP). This bit controls whether the TAP special function pins are enabled. The TAP defaults
to being enabled. See
Section 10 for more information on this bit.
0 = JTAG/TAP functions are disabled and P0.0–P0.3 can be used as general-purpose I/O pins
1 = TAP special function pins P0.0–P0.3 are enabled to act as JTAG inputs and outputs
Bits 6 and 0: Reserved
Bits 5 and 4: Code Data Access Bits 1 and 0 (CDA1:CDA0). See Section 1 for more information on these bits.
Bit 3: Upper Program Access (UPA). See Section 1 for more information on this bit.
Bit 2: ROM Operation Done (ROD). This bit is used to signify completion of a ROM operation sequence to the control units. This allows
the debug engine to determine the status of a ROM sequence. Setting this bit to logic 1 causes an internal system reset if the SPE bit
is also set. Setting the ROD bit will clear the SPE bit if it is set and the ROD bit will be automatically cleared by hardware once the con-
trol unit acknowledges the done indication.
Bit 1: Password Lock (PWL). This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte password to be
matched with the password in the program space before allowing access to the password protected in-circuit debug or bootstrap
loader ROM routines. Clearing this bit to 0 disables the password protection for these ROM routines. See
Section 12 for more infor-
mation on this bit.
MAXQ7665/MAXQ7666 User’s Guide
11-9
Bit # 7 6 5 4 3 2 1 0
Name TAP — CDA1 CDA0 UPA ROD PWL —
Reset 1 0 0 0 0 0 1* 0
Access rw r rw rw rw rw rw r
r = read, w = write
*
This register defaults to 80h on all forms of reset except after power-on reset. After power-on reset, the PWL bit is also set and this register defaults to 82h.
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