Maxim Integrated MAXQ7666 - Manual (Page 244)

MAXQ7665/MAXQ7666 User’s Guide
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Bit 6: Type 2 Timer Output Enable 0 (T2OE0). This register bit enables the timer output function for the external Tx pin. The follow-
ing table shows the timer output possibilities for the external pin. Note: When the timer output function on the Tx pin is enabled, the
polarity bit (T2POL0) selects the starting logic level for the pin output.
Bit 5: Type 2 Timer Polarity Select 0 (T2POL0). When the timer output function has been enabled (T2OE0 = 1), the polarity select bit
defines the starting logic level for the Tx output waveform. When T2POL0 = 0, the starting state for the output is logic-low. When
T2POL0 = 1, the starting state for the output is logic-high. The T2POL0 bit can be modified at any time, but takes effect on the exter-
nal pin when T2OE0 is changed from 0 to 1. When the Type 2 timer pin is being used as an input (T2OE0 = 0), the polarity select bit
defines which logic level can be used to gate the timer input clock (when CCF1:CCF0
≠ 11b). When CCF1:CCF0 = 11b, T2POL0
defines which edge can start/stop a single-shot capture and which edge reload can be skipped (if CPRL2 = 1 and G2EN = 1).
Note: The MAXQ7665/MAXQ7666 timer 2 does not support an input/output pin and serves only as an internal timer. Thus, polarity
select functionality does not apply for timer 2.
Bit 4: Type 2 Timer Low Run Enable (TR2L). This bit start/stops the low 8-bit timer (T2Lx) when dual 8-bit mode (T2MD = 1) is in
effect. This bit has no effect when T2MD = 0.
0 = timer low stopped
1 = timer low run
Bit 3: Type 2 Timer Run Enable (TR2). This bit starts/stops the Type 2 timer. In the dual 8-bit mode of operation, this bit applies only
to the T2Hx timer/counter. Otherwise, the bit applies to the full 16-bit T2Vx timer/counter. When the timer is stopped (TR2 = 0), the timer
registers hold their count. The single-shot bit (SS2) can override and/or delay the effect of the TR2 bit.
0 = timer stopped
1 = timer run
Bit 2: Capture and Reload Enable (CPRL2). This bit enables a reload (in addition to a capture) on the edge specified by CCF1:CCF0
when operating in capture/reload mode (C/T2 = 0). If both edges are defined for capture/reload (CCF1:CCF0 = 11b), enabling the gat-
ing control (G2EN = 1) allows the T2POL0 bit to be used to prevent a reload on one of the edges; if T2POL0 is 0, no reload on the
falling edge; or, if T2POL0 is 1, no reload on the rising edge.
0 = capture on edge(s) specified by CCF1:CCF0 bits
1 = capture and reload on edge(s) specified by CCF1:CCF0 bits
Bit 1: Single-Shot (SS2). This bit is used to automatically override or delay the effect of the TR2 bit setting. The single-shot bit is only
useful in the timer mode of operation (C/T2 = 0) and should not be set to 1 when the counter mode of operation is enabled (C/T2 = 1).
Compare Mode: If SS2 is written to 1 while in compare mode, one cycle of the defined waveform (reload to overflow) is output to
the Tx pin as prescribed by T2POL0 and T2OE0 controls. The only time that this does not immediately occur is when a gating con-
dition is also defined. If a gating condition is defined, the single-shot cycle cannot occur until the gating condition is removed. If
the specified nongated level is already in effect, the single-shot period starts. The gated single-shot output is not supported in dual
8-bit mode.
Capture Mode: If SS2 is written to 1 while in capture mode, the timer is halted and the single-shot capture cycle does not begin
until 1) the edge specified by CCF1:CCF0 is detected, or 2) the defined gating condition is removed. Once running, the timer con-
tinues running (as allowed by the gate condition) until the defined capture single-shot edge is detected. In this way, the SS2 bit
can be used to delay the running of a timer until an edge is detected (setting both SS2 and TR2 = 1) or override the TR2 = 0 bit
setting for one capture cycle (setting only SS2 = 1). When both edges are defined for capture (CCF1:CCF0 = 11b), the T2POL0
bit serves to define the single-shot start/end edge: falling edge if T2POL0 = 1, rising edge if T2POL0 = 0. No interrupt flag is set
when the starting edge for the single-shot capture cycle is detected. The single-shot capture cycle always ends when the next
single-shot edge is detected. The start/end edge is defined by T2POL0. This bit is intended to automate pulse-width measurement
(low or high) and duty cycle/period measurement.
Note: The MAXQ7665/MAXQ7666 timer 2 does not support an input/output pin and serves only as an internal timer. Thus, some
single-shot functionality does not apply for timer 2.
T2OE0 T2MD TIMER INPUT/OUTPUT PIN (Tx)
0 X Port latch data
1 0 16-bit PWM output
1 1 8-bit PWM output (T2Hx)
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