Maxim Integrated MAXQ7666 - Manual (Page 84)

MAXQ7665/MAXQ7666 User’s Guide
2-12
2.4 Linear Regulator
The MAXQ7665/MAXQ7666 contain a +3.3V, low dropout (LDO) linear regulator. The regulator powers the MAXQ7665/MAXQ7666 dig-
ital core functions including the CPU, flash, SRAM, oscillator, and all the digital peripherals. The linear regulator is powered by the +5V
DVDDIO supply. The
REGEN signal must be connected to GNDIO to enable the internal regulator. When the internal linear regulator is
disabled ( REGEN connected to DVDDIO), an external +3.3V supply must be used.
2.5 Power-On Reset
The MAXQ7665/MAXQ7666 support an on-chip power-on reset (POR) circuit to ensure proper initialization of internal device states. The
POR circuit provides a power-on rising voltage threshold and a minimum power-on delay sufficient to accomplish this initialization. When
power is first applied to the MAXQ7665/MAXQ7666, the MAXQ7665/MAXQ7666 are held in a power-on reset state (Figure 2-4). The
MAXQ7665/MAXQ7666 power-on circuitry (POR) monitors the DVDD supply voltage in relation to the on-chip band gap voltage reference.
On power-up, once DVDD exceeds ~1.2V, the
RESET pin is asserted to be logic-low. All the internal system and peripheral registers are
reset if DVDD from cold start exceeds ~1.2. Also, above this voltage, the power-on-reset delay counter is started.
For the MAXQ7665/MAXQ7666 to exit power-on reset, the following two conditions must apply:
• DVDD is above the power-on-reset rising voltage threshold level V RST (2.7V–2.99V power-on default)
• The internal RC oscillator has completed 65,536 cycles (power-on-reset delay for power supply to stabilize; about 8.6ms at 7.6MHz)
Once the power-up period has elapsed, the reset condition is removed automatically ( RESET pin goes high) and software execution will
begin at the reset vector location 8000h (in the utility ROM). Software can determine whether a reset was caused by a power-on reset by
checking the POR flag in the WDCN register. This flag is set to 1 following a power-on reset, and should be cleared by software after it
has been checked.
Figure 2-4. MAXQ7665/MAXQ7666 Power-On Reset
POWER-UP DELAY (65,536 RC CYCLES
OR 8.6ms AT 7.6MHz)
INTERNAL RESET
NOMINAL DVDD
(+3.3V)
V RST
(+2.7V)
+1.2V
DGND
INTERNAL
RC
STARTUP TIME
RESET PIN
Note: In a brownout reset (BOR) situation (see Section 2.5.2), where the voltage drops below the DVDD BOR threshold (e.g., 2.7V) and
rises back above the default power-on-reset rising voltage threshold level (2.7V), the POR flag in WDCN register will not be set unless
DVDD drops below ~1.2V. The POR flag will be set if DVDD voltage drops below ~1.2V and rises back above the default POR rising
voltage threshold (2.7V). In such a case, the MAXQ7665/MAXQ7666 go through a complete POR reset as described above.
Maxim Integrated