Maxim Integrated MAXQ7666 - Manual (Page 283)

MAXQ7665/MAXQ7666 User’s Guide
9-10
9.3.2 SPI Slave Operation
The MAXQ7665/MAXQ7666 SPI module operates in slave mode when the MSTM bit is cleared to logic 0. In slave mode, the SPI mod-
ule is dependent on the SCLK signal sourced from the master to control the data transfer. The SCLK input frequency should be no
greater than the system clock of the MAXQ7665/MAXQ7666 slave device divided by 8.
The slave select ( SS) input must be externally asserted by a master before data exchange can take place. SS must be low before
data transaction begins and must remain low for the duration of the transaction. If data is to be transmitted by the slave device, it
must be written to its shift register before the beginning of a transfer cycle, otherwise the character already in the shift register will be
transferred. The slave device considers a transfer to begin with the first clock edge or the falling edge of
SS, dependent on the data
transfer format.
The SPI slave receives data from the external master MOSI pin, most significant bit first, while simultaneously transferring the contents
of its shift register to the master on the MISO pin, also most significant bit first. Data received from the external master replaces data
in the internal shift register until the transfer completes. Just like the master mode of operation, received data is loaded into the read
buffer and the SPI transfer complete flag is set at the end of transfer. The setting of the transfer complete flag generates an interrupt
request if enabled.
When SS is not asserted, the slave device ignores the SCLK clock and the shift register is disabled. Under this condition, the device
is basically idle, no data is shifted out from the shift register, and no data is sampled from the MOSI pin. The MISO pin is placed in an
input mode and is weakly pulled high to allow other devices on the bus to drive the bus. Deassertion of the
SS signal by the master
during a transfer (before a full character, as defined by the CHR, is received) aborts the current transfer. When the transfer is aborted
no data is loaded into the read buffer, the SPIC flag is not set, and the slave logic and bit counter are reset.
In slave mode, the clock divide ratio bits (CKR7:CKR0) have no function since an external master supplies the serial clock. The trans-
fer format (CKPOL, CKPHA settings) and the character length selection (CHR) for the slave device, however, should match the master
for proper communication.
Maxim Integrated