Maxim Integrated MAXQ7666 - Manual (Page 193)

MAXQ7665/MAXQ7666 User’s Guide
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4.14 BUSON/BUSOFF Recovery and Error Counter Operation
The CAN module contains two peripheral registers that allow software to monitor and modify (under controlled conditions) the error
counts associated with the transmit- and receive-error counters in the CAN module. These registers can be read at any time. Writing
the CAN transmit-error counter registers updates both the transmit-error counter registers and the receive-error counter registers with
the same value. Details are given in the peripheral registers description. These counters are incremented or decremented according
to CAN specification version 2.0B, summarized in Table 4-3. The error counters are initialized by a CRST = 1 or a system reset to 00h.
The error counters remain unchanged when the CAN module enters and exits from a low-power mode through the SIESTA or PDE bit.
Changes to the error counters are performed according to the following rules. This level of detail is not necessary for the average CAN
user, and full information is provided in the CAN2.0B specification. More than one rule can apply to a given message.
Table 4-3. Rules for Changes to Error Counters
A node is error-active when the transmit- and receive-error counters are less than 128. When in an error-active state, an error condi-
tion causes the node to send an error frame on the bus. A node is error-passive when the transmit-error count equals or exceeds 128,
or when the receive-error count equals or exceeds 128. An error-passive node does not transmit an error frame on the bus. An error-
passive node becomes error-active again when both the transmit-error count and the receive-error count are less than or equal to 127.
A node is BUSOFF when the transmit-error count is greater than or equal to 256. A BUSOFF node becomes error-active (no longer
BUSOFF) when its error counters are both set to 0 and after 128 occurrences of 11 consecutive recessive bits have been monitored
on the bus.
After exceeding the error-passive limit (128), the receive-error counter is not increased any further. When a message is received cor-
rectly, the counter is set again to a value between 119 and 127 (compare with CAN2.0B specification). After reaching BUSOFF status,
the transmit-error counter is undefined while the receive-error counter is cleared and changes its function. The receive-error counter is
incremented after every 11 consecutive recessive bits on the bus. These 11 bits correspond to the gap between two messages on the
bus. If the receive-error counter reaches count = 128 following the BUSOFF recovery sequence, the CAN module changes automati-
cally back to the status of BUSON and then sets SWINT = 1. After setting SWINT, all internal flags of the CAN module are reset and
the error counters are cleared. A recovery from a BUSOFF condition does not alter any of the previously programmed dual port mem-
ory values or peripheral registers, apart from the transmit- and receive-error peripheral registers and the error conditions displayed in
CAN status register. The bus timing remains as previously programmed.
CONDITION EFFECT ON ERROR COUNTERS
Error detected by receiver, unless the detected error was a bit error during the sending of
an active error flag or an overload flag.
Receive-error counter incremented by 1.
Receiver detects a dominant bit as the first bit after sending an error flag. Receive-error counter incremented by 8.
Transmitter sends an error flag. Note, however, that the transmit-error count does not
change if:
(1) The transmitter is error passive and detects an acknowledgement error because of not
detecting a dominant acknowledge, and does not detect a dominant bit while sending its
passive error flag.
(2) Or, if the transmitter sends an error flag because a stuff error occurred during arbitration,
and has been sent as recessive, but monitored as dominant.
Transmit-error counter incremented by 8.
Transmitter detects a bit error while sending an active error flag or an overload flag. Transmit-error counter incremented by 8.
Receiver detects a bit error while sending an active error flag or an overload flag. Receive-error counter incremented by 8.
Node detects the 14th consecutive dominant bit (in case of an active error flag or an
overload flag), or detects the 8th consecutive dominant bit following a passive error flag, or
after a sequence of additional eight consecutive dominant bits.
Transmit-error counter incremented by 8. Receive-error
counter incremented by 8.
Message is successfully transmitted (acknowledge received and no error until end of frame
is complete). Transmit-error counter is decremented by 1 (unless it
was already 0).
A message has been successfully received (reception without error up to the acknowledge
slot and the successful sending of the acknowledge bit), and the receive-error count was
between 1 and 127.
Receive-error counter decremented by 1.
A message has been successfully received (reception without error up to the acknowledge
slot and the successful sending of the acknowledge bit), and the receive-error count was
greater than 127.
Receive-error counter is set to a value between 119
and 127.
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