Maxim Integrated MAXQ7666 - Manual (Page 200)

MAXQ7665/MAXQ7666 User’s Guide
5-3
SECTION 5: OSCILLATOR/CLOCK GENERATION MODULE
The MAXQ7665/MAXQ7666 oscillator/clock generation module supplies the system clock for the microcontroller core and all the
peripheral modules. The MAXQ7665/MAXQ7666 are designed to operate up to 8MHz. Except where explicitly stated, the MAXQ7665
and MAXQ7666 have identical features.
The MAXQ7665/MAXQ7666 oscillator/clock generation module features include:
• Internal 7.6MHz RC oscillator
• Internal high-frequency oscillator, using an external crystal or resonator (up to 8MHz)
• External high-frequency clock signal (up to 8MHz)
• External crystal-fail detection and automatic switchover
• Power-up timer
• Power-saving management modes
• Watchdog timer
5.1 Architecture
Figure 5-1 shows a simplified functional block diagram of the MAXQ7665/MAXQ7666 oscillator/clock generation module. All function-
al modules in the MAXQ7665/MAXQ7666 are synchronized to a single system clock except the watchdog timer, which always oper-
ates using the internal, undivided 7.6MHz RC oscillator. The internal clock circuitry generates the system clock from one of three pos-
sible sources:
• Internal 7.6MHz RC oscillator
• Internal high-frequency oscillator, using an external crystal or resonator
• External high-frequency clock signal
These options provide the flexibility to select the clock source that best fits a particular application. The external crystal and clock are
mutually exclusive since they share a common pin. The internal 7.6MHz RC oscillator provides a low-cost system solution that elimi-
nates the need for a high-frequency crystal in some applications. The clock source selection is determined by the state of the XT bit
in the CKCN register. When XT = 0, the internal 7.6MHz RC oscillator is used for clock generation; when XT = 1, the clock source is
from external, either from an external clock or a crystal depending on the user system configuration. The internal 7.6MHz RC oscilla-
tor is selected as the default clock source on a power-on reset condition.
When the device is powered up, the power-on reset circuitry holds the device in reset to:
• Start up the internal 7.6MHz RC oscillator
• Reset the power-up counter, and
• Allow power-up delay of 65,536 internal 7.6MHz RC oscillator cycles (8.6ms typical) before releasing the reset and starting CPU
operation
The oscillator/clock generation module includes a clock divider (CD1:CD0 bits) to select the number of oscillator clock source cycles
per system clock. By default, one system clock is generated for every two oscillator cycles (divide by 2). Maximum performance is
achieved by changing this to one system clock for each oscillator cycle (divide by 1).
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