Maxim Integrated MAXQ7666 - Manual (Page 241)

7.1.1 Type 2 Timer/Counter I/O Pins
Each Type 2 timer/counter module normally supports one primary input/output pin that is referred to as Tx. Table 7-1 describes the pin
assignments for the three MAXQ7665/MAXQ7666 timer/counter modules.
Table 7-1. Type 2 Timer/Counter Input and Output Pins
7.2 Type 2 Timer/Counter Peripheral Registers
The MAXQ7665/MAXQ7666 provide three Type 2 timer/counter modules: timer 0, timer 1, and timer 2. Table 7-2 shows the associated
peripheral registers for these timer/counter modules.
Table 7-2. Type 2 Timer/Counter Peripheral Registers
MAXQ7665/MAXQ7666 User’s Guide
7-6
PIN
TIMER/COUNTER
EXTERNAL SIGNAL
48 56
MULTIPLEXED
WITH PORT PIN
FUNCTION
T0—Timer 0
Input/Output
24 27 P0.6
Timer 0 Input/Output. T0 is shared with GPIO port P0 bit 6. As timer 0 input/output, the
pin supports clock gating, capture/compare, counter, and PWM functionalities.
T1—Timer 1
Input/Output
25 29 P0.7
Timer 1 Input/Output. T1 is shared with GPIO port P0 bit 7. As timer 1 input/output, the
pin supports clock gating, capture/compare, counter, and PWM functionalities.
ADDRESS
TIMER/COUNTER
REGISTER
TIMER 0 TIMER 1 TIMER 2
FUNCTION
Configuration Register
T2CFG0
M2[10h] T2CFG1
M2[11h] T2CFG2
M3[10h] Controls counter/timer select, capture/compare function select,
8-bit/16-bit mode select, and clock divide modes
Control Register A
T2CNA0
M2[0h]
T2CNA1
M2[04h] T2CNA2
M3[0h]
I/O settings, run enables, polarity modes
Control Register B
T2CNB0
M2[08h] T2CNB1
M2[0Ch] T2CNB2
M3[08h]
Contains capture, compare, overflow flags
Value Register
T2V0
M2[09h]
T2V1
M2[0Dh]
T2V2
M3[09h]
Holds current timer value
Value MSB Register
T2H0
M2[01h]
T2H1
M2[05h]
T2H2
M3[01h]
Provides access to high byte of T2Vx
Reload Register
T2R0
M2[0Ah]
T2R1
M2[0Eh]
T2R2
M3[0Ah]
Holds timer reload value
Reload MSB Register
T2RH0
M2[02h]
T2RH1
M2[06h]
T2RH2
M3[02h]
Provides access to high byte of T2Rx
Capture/Compare
Register
T2C0
M2[0Bh]
T2C1
M2[0Fh]
T2C2
M3[0Bh]
Holds capture/compare value
Capture/Compare MSB
Register
T2CH0
M2[03h]
T2CH1
M2[07h]
T2CH2
M3[03h]
Access to high byte of T2Cx
Note: In the MAXQ7665/MAXQ7666, the timer 2 input/output signal, T2, is not supported on the 48- and 56-pin packages. Thus, timer 2 can serve only as an
internal timer.
Maxim Integrated