Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 101)

Chapter 6: Functional Description—High-Performance Controller II 6–7
Controller Features Descriptions
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
■ Has a latency increase of one clock for both writes and reads.
■ For a 128-bit interface, ECC is generated as one 64-bit data path with 8-bits of ECC
path, plus a second 64-bit data path with 8-bits of ECC path.
■ Detects and corrects all single-bit errors.
■ Detects all double-bit errors.
■ Counts the number of single-bit and double-bit errors.
■ Accepts partial writes, which trigger a read-modify-write cycle, for memory
devices with DM pins.
■ Can inject single-bit and double-bit errors to trigger ECC correction for testing and
debugging purposes.
■ Generates an interrupt signal when an error occurs.
1 When using ECC, you must initialize memory before writing to it.
When a single-bit or double-bit error occurs, the ECC logic triggers the ecc_interrupt
signal to inform you that an ECC error has occurred. When a single-bit error occurs,
the ECC logic reads the error address, and writes back the corrected data. When a
double-bit error occurs, the ECC logic does not do any error correction but it asserts
the local_rdata_error signal to indicate that the data is incorrect. The
local_rdata_error
signal follows the same timing as the local_rdata_valid signal.
Enabling autocorrection allows the ECC logic to delay all controller pending activities
until the correction completes. You can disable autocorrection and schedule the
correction manually when the controller is idle to ensure better system efficiency. To
manually correct ECC errors, follow these steps:
1. When an interrupt occurs, read out the SBE_ERROR register. When a single-bit error
occurs, the SBE_ERROR register is equal to one.
2. Read out the ERR_ADDR register.
3. Correct the single-bit error by issuing a dummy write to the memory address
stored in the ERR_ADDR register. A dummy write is a write request with the
local_be
signal zero, that triggers a partial write which is effectively a
read-modify-write event. The partial write corrects the data at that address and
writes it back.
Partial Writes
The ECC logic supports partial writes. Along with the address, data, and burst
signals, the Avalon-MM interface also supports a signal vector, local_be, that is
responsible for byte-enable. Every bit of this signal vector represents a byte on the
data-bus. Thus, a logic low on any of these bits instructs the controller not to write to
that particular byte, resulting in a partial write. The ECC code is calculated on all
bytes of the data-bus. If any bytes are changed, the IP core must recalculate the ECC
code and write the new code back to the memory.
For partial writes, the ECC logic performs the following steps:
1. The ECC logic sends a read command to the partial write address.