Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 132)

8–
4
Ch
apt
er
8:
T
imin
g
Diagr
a
ms
D
D
R
an
d DDR
2 Hi
gh
-P
erfo
rmance Controllers
II
Ex
ternal Memory
Interfac
e H
andbook
Volu
me 3
Jun
e
2
011
Al
tera Cor
por
atio
n
Secti
o
n
I.
D
DR an
d DDR
2 SDR
A
M Co
ntr
o
lle
rs with ALTMEMPH
Y IP
User G
u
ide
Half-Rate Write
Figure 8–2. Half-Rate Write Operation for HPC II
Local Interface
local_address[25:0]
local_size[4:0]
local_ready
local_burstbegin
local_be[3:0]
local_write_req
local_wdata[31:0]
afi_addr[27:0]
Controller - AFI
afi_ba[5:0]
afi_cs_n[3:0]
AFI Command[2:0]
afi_dm[3:0]
afi_wlat[4:0]
afi_dqs_burst[0]
afi_dqs_burst[1]
afi_wdata[31:0]
afi_wdata_valid[1:0]
mem_cke[1:0]
AFI Memory Interface
mem_clk
mem_ba[2:0]
mem_addr[13:0]
mem_cs_n[0]
Mem Command[2:0]
mem_dqs
mem_dm
mem_dq[7:0]
mem_odt[1:0]
phy_clk
0000002 0000000 0000004 0000000
2
[1] [2] [3] [4] [5] [6]
AABBCCDD AABBCCDD AABBCCDD EEFF0011 EEFF0011 EEFF0011
AABBCCDD AABBCCDD AABBCCDD EEFF0011 EEFF0011 EEFF0011
0000000 0000000 0000000 0000000 0000008 0000000 0000010 0000000
B F B F B F B F F
F
B
ACT NOP WR NOP WR NOP WR NOP NOP WR
0 F F
2
0
3 0 3
0000 0000 0000 0000 0008 0000 0010
NOP ACT NOP WR NOP NOP NOP NOP WR WR WR
00 00 DD CC BB AA 11 00 FF EE DD CC BB AA 11 00 FF EE DD CC BB AA 11 00 FF EE