Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 23)

Chapter 2: Getting Started 2–9
Generated Files
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 2–4 shows the modules that are instantiated in the
< variation_name>_alt_mem_phy.v/.vhd file. A particular ALTMEMPHY variation
may or may not use any of the modules, depending on the memory standard that you
specify.
<variation_name>_alt_mem_phy_pll.qip
Quartus II IP file for the PLL that your ALTMEMPHY
variation uses that contains the files associated with
this megafunction.
<variation_name>_alt_mem_phy_pll_bb.v/.cmp
Black box file for the PLL used in your ALTMEMPHY
variation. Typically unused.
<variation_name>_alt_mem_phy_reconfig.qip
Quartus II IP file for the PLL reconfiguration block.
Only generated when targeting Arria GX, HardCopy II,
Stratix II, and Stratix II GX devices.
<variation_name>_alt_mem_phy_reconfig.v/.vhd
PLL reconfiguration block module. Only generated
when targeting Arria GX, HardCopy II, Stratix II, and
Stratix II GX devices.
<variation_name>_alt_mem_phy_reconfig_bb.v/cmp
Black box file for the PLL reconfiguration block. Only
generated when targeting Arria GX, HardCopy II,
Stratix II, and Stratix II GX devices.
<variation_name>_bb.v/.cmp
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
<variation_name>_ddr_pins.tcl
Contains procedures used in the
<variation_name>_ddr_timing.sdc and
<variation_name>_report_timing.tcl files.
<variation_name>_pin_assignments.tcl
Contains I/O standard, drive strength, output enable
grouping, DQ/DQS grouping, and termination
assignments for your ALTMEMPHY variation. If your
top-level design pin names do not match the default
pin names or a prefixed version, edit the assignments
in this file.
<variation_name>_ddr_timing.sdc
Contains timing constraints for your ALTMEMPHY
variation.
<variation_name>_report_timing.tcl
Script that reports timing for your ALTMEMPHY
variation during compilation.
Table 2–3. ALTMEMPHY Generated Files (Part 2 of 2)
File Name Description
Table 2–4. Modules in <variation_name>_alt_mem_phy.v File (Part 1 of 2)
Module Name Usage Description
<variation_name>_alt_mem_phy_ad
dr_cmd
All ALTMEMPHY variations Generates the address and command structures.
<variation_name>_alt_mem_phy_cl
k_reset
All ALTMEMPHY variations Instantiates PLL, DLL, and reset logic.
<variation_name>_alt_mem_phy_dp
_io
All ALTMEMPHY variations Generates the DQ, DQS, DM, and QVLD I/O pins.
<variation_name>_alt_mem_phy_mi
mic DDR2/DDR SDRAM
ALTMEMPHY variation Creates the VT tracking mechanism for DDR and
DDR2 SDRAM PHYs.