Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 20)

2–6 Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
1 To ensure that the external connections and memory interfaces are
exported to the top-level RTL file, be careful not to accidentally rename or
delete either of these interfaces in the Export column of the System
Contents
tab.
1 Among the files generated by Qsys is the Quartus II IP File (.qip). This file
contains information about a generated IP core or system. In most cases, the
.qip
file contains all of the necessary assignments and information required
to process the MegaCore function or system in the Quartus II compiler.
Generally, a single .qip file is generated for each Qsys system. However,
some more complex Qsys components generate a separate .qip file. In that
case, the system .qip file references the component .qip file.
Compile your design, refer to “Compiling and Simulating” on page 4–1 .
MegaWizard Plug-In Manager Flow
The MegaWizard Plug-In Manager flow allows you to customize the DDR or DDR2
SDRAM Controller with ALTMEMPHY or the stand-alone PHY with the
ALTMEMPHY megafunction, and manually integrate the function into your design.
f For more information about the MegaWizard Plug-In Manager, refer to the Quartus II
Help.
Specifying Parameters
To specify parameters using the MegaWizard Plug-In Manager flow, perform the
following steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
Wizard .
2. On the Tools menu, click MegaWizard Plug-In Manager to start the MegaWizard
Plug-In Manager.
■ The DDR or DDR2 SDRAM Controller with ALTMEMPHY is in the Interfaces
folder under the External Memory folder.
■ The ALTMEMPHY megafunction is in the I/O folder.
1
The <variation name> must be a different name from the project name and
the top-level design entity name.
3. Specify the parameters on all pages in the Parameter Settings tab.
f
For detailed explanation of the parameters, refer to the “Parameter
Settings” on page 3–1 .
4. On the EDA tab, turn on Generate simulation model to generate an IP functional
simulation model for the MegaCore function in the selected language.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.