Release information, Device family support, Release information –2 device family support –2 – Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP User Manual

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Chapter 1: About This IP

Release Information

External Memory Interface Handbook Volume 3

June 2011

Altera Corporation

Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide

Release Information

Table 1–1

provides information about this release of the DDR and DDR2 SDRAM

high-performance controller and ALTMEMPHY IP.

Altera verifies that the current version of the Quartus

®

II software compiles the

previous version of each MegaCore function. The

MegaCore IP Library Release Notes

and Errata

report any exceptions to this verification. Altera does not verify

compilation with MegaCore function versions older than one release. For information
about issues on the DDR and DDR2 SDRAM high-performance controllers and the
ALTMEMPHY megafunction in a particular Quartus II version, refer to the

Quartus II

Software Release Notes

.

Device Family Support

The MegaCore functions provide either final or preliminary support for target Altera
device families:

Final support

means the core is verified with final timing models for this device

family. The core meets all functional and timing requirements for the device family
and can be used in production designs.

Preliminary support

means the core is verified with preliminary timing models

for this device family. The core meets all functional requirements, but might still be
undergoing timing analysis for the device family. It can be used in production
designs with caution.

HardCopy Compilation

means the core is verified with final timing models for

the HardCopy

®

device family. The core meets all functional and timing

requirements for the device family and can be used in production designs.

HardCopy Companion

means the core is verified with preliminary timing models

for the HardCopy companion device. The core meets all functional requirements,
but might still be undergoing timing analysis for HardCopy device family. It can
be used in production designs with caution.

Table 1–1. Release Information

Item

Description

Version

11.0

Release Date

May 2011

Ordering Codes

IP-SDRAM/HPDDR (DDR SDRAM HPC)

IP-SDRAM/HPDDR2 (DDR2 SDRAM HPC)

IP-HPMCII (HPC II)

Product IDs

00BE (DDR SDRAM)

00BF (DDR2 SDRAM)

00CO (ALTMEMPHY Megafunction)

Vendor ID

6AF7

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