Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 98)

6–4 Chapter 6: Functional Description—High-Performance Controller II
Controller Features Descriptions
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
CSR Interface
The CSR interface provides communication with your system’s internal control status
registers.
Controller Features Descriptions
The following sections describe main features of the memory controller.
Data Reordering
The controller implements data reordering to maximize efficiency for read and write
commands. The controller can reorder read and write commands as necessary to
mitigate bus turn-around time and reduce conflict between rows.
Inter-bank data reordering reorders commands going to different bank addresses.
Commands going to the same bank address are not reordered. This reordering
method implements simple hazard detection on the bank address level.
The controller implements logic to limit the length of time that a command can go
unserved. This logic is known as starvation control. In starvation control, a counter is
incremented for every command served. You can set a starvation limit, to ensure that
a waiting command is served immediately, when the starvation counter reaches the
specified limit.
Pre-emptive Bank Management
Data reordering allows the controller to issue bank-management commands
pre-emptively, based on the patterns of incoming commands; consequently, the
desired page in memory can be already open when a command reaches the AFI
interface.
Quasi-1T and Quasi-2T
One controller clock cycle equals two memory clock cycles in a half-rate interface, and
to four memory clock cycles in a quarter-rate interface. To fully utilize the command
bandwidth, the controlller can operate in Quasi-1T half-rate and Quasi-2T
quarter-rate modes.
In Quasi-1T and Quasi-2T modes, the controller issues two commands on every
controller clock cycle. The controller is constrained to issue a row command on the
first clock phase and a column command on the second clock phase, or vice versa.
Row commands include activate and precharge commands; column commands
include read and write commands.
User Autoprecharge Commands
The autoprecharge read and autoprecharge write commands allow you to indicate to
the memory device that this read or write command is the last access to the currently
open row. The memory device automatically closes or autoprecharges the page it is
currently accessing so that the next access to the same bank is quicker.
This command is useful for applications that require fast random accesses.