Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 107)

Chapter 6: Functional Description—High-Performance Controller II 6–13
Top-Level Signals Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Table 6–7. Local Interface Signals (Part 1 of 4)
Signal Name Direction Description
local_address[] Input
Memory address at which the burst should start.
By default, the IP core maps local address to the bank interleaving scheme.
You can change the ordering via the Local-to-Memory Address Mapping
option in the Controller Settings page.
The IP core sizes the width of this bus according to the following equations:
■ Full rate controllers
For one chip select: width = row bits + bank bits + column bits – 1
For multiple chip selects: width = chip bits + row bits + bank bits + column
bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, the local address is 24 bits wide. To map local_address to bank, row
and column address:
local_address is 24 bits wide
local_address[23:11] = row address[12:0]
local_address[10:9] = bank address [1:0]
local_address [8:0] = column address[9:1]
The IP core ignores the least significant bit (LSB) of the column address
(multiples of four) on the memory side, because the local data width is twice
that of the memory data bus width.
■ Half rate controllers
For one chip select: width = row bits + bank bits + column bits – 2
For multiple chip selects: width = chip bits + row bits + bank bits + column
bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10 bits
wide, the local address is 23 bits wide. To map local_address to bank, row
and column address:
local_address is 23 bits wide
local_address[22:10] = row address[12:0]
local_address[9:8] = bank address [1:0]
local_address [7:0] = column address[9:2]
The IP core ignores two LSBs of the column address on the memory side,
because the local data width is four times that of the memory data bus width.
local_be[] Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be
is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm, consider a
full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be = < 1100 >< 0110 >< 1010 >
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >