Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 108)

6–14 Chapter 6: Functional Description—High-Performance Controller II
Top-Level Signals Description
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
local_burstbegin Input
The Avalon burst begin strobe, which indicates the beginning of an Avalon
burst. Unlike all other Avalon-MM signals, the burst begin signal does not
stay asserted if local_ready is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even if the
slave deasserts local_ready. The IP core samples this signal at the rising
edge of phy_clk when local_write_req is asserted. After the slave
deasserts the local_ready signal, the master keeps all the write request
signals asserted until local_ready signal becomes high again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and local_address from which the data should be read
is given to the memory. After the slave deasserts local_ready
(waitrequest_n in Avalon interface), the master keeps all the read request
signals asserted until local_ready becomes high again.
local_read_req Input
Read request signal. You cannot assert read request and write request
signals at the same time. The controller must deassert reset_phy_clk_n
before you can assert local_autopch_req.
local_refresh_req Input
User-controlled refresh request. If Enable User Auto-Refresh Controls
option is turned on, local_refresh_req becomes available and you are
responsible for issuing sufficient refresh requests to meet the memory
requirements. This option allows complete control over when refreshes are
issued to the memory including grouping together multiple refresh
commands. Refresh requests take priority over read and write requests,
unless the IP core is already processing the requests.
local_refresh_chip Input
Controls which chip to issue the user refresh to. The IP core uses this active
high signal with local_refresh_req. This signal is as wide as the memory
chip select. This signal asserts a high value to each bit that represents the
refresh for the corresponding memory chip.
For example: If local_refresh_chip signal is assigned with a value of
4’b0101
, the controller refreshes the memory chips 0 and 2, and memory
chips 1 and 3 are not refreshed.
local_size[] Input
Controls the number of beats in the requested read or write access to
memory, encoded as a binary number. The IP core supports Avalon burst
lengths from 1 to 64. The IP core derives the width of this signal based on the
burst count that you specify in the Local Maximum Burst Count option. With
the derived width, you specify a value ranging from 1 to the local maximum
burst count specified.
local_wdata[] Input
Write data bus. The width of local_wdata is twice that of the memory data
bus for a full-rate controller; four times the memory data bus for a half-rate
controller.
local_write_req Input
Write request signal. You cannot assert read request and write request signal
at the same time. The controller must deassert reset_phy_clk_n before
you can assert local_write_req.
Table 6–7. Local Interface Signals (Part 2 of 4)
Signal Name Direction Description