Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 51)

Chapter 5: Functional Description—ALTMEMPHY 5–5
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Stratix III and Stratix IV Devices
The address and command clock in Stratix III and Stratix IV devices is one of the PLL
dedicated clock outputs whose phase can be adjusted to meet the setup and hold
requirements of the memory clock. The Stratix III address and command clock,
ac_clk_1x
, is half rate. The command and address pins use the DDIO output circuitry
to launch commands from either the rising or falling edges of the clock. The chip
select (cs_n) pins and ODT are only enabled for one memory clock cycle and can be
launched from either the rising or falling edge of ac_clk_1x signal, while the address
and other command pins are enabled for two memory clock cycles and can also be
launched from either the rising or falling edge of ac_clk_1x signal.
The full-rate address and command datapath is the same as that of the half-rate
address and command datapath, except that there is no full-rate to half-rate
conversion in the IOE. The address and command signals are full-rate here.
Clock and Reset Management
This topic describes the clock and reset management for specific device types.
Arria GX, Arria II GX, HardCopy II, Stratix II, and Stratix II GX Devices
The clocking and reset block is responsible for clock generation, reset management,
and phase shifting of clocks. It also has control of clock network types that route the
clocks.
Clock Management
The clock management feature allows the ALTMEMPHY megafunction to work out
the optimum resynchronization clock phase during calibration, and track the system
voltage and temperature (VT) variations. Clock management is achieved by
phase-shifting the clocks relative to each other.
Clock management circuitry is implemented by the following device resources:
■ PLL
■ PLL reconfiguration
■ DLL
PLL
The ALTMEMPHY parameter editor automatically generates an ALTPLL
megafunction instance. The ALTPLL megafunction is responsible for generating the
different clock frequencies and relevant phases used within the ALTMEMPHY
megafunction.
The minimum PHY requirement is to have 16 phases of the highest frequency clock.
The PLL uses the With No Compensation option to minimize jitter.
You must choose a PLL and PLL input clock pin that are located on the same side of
the memory interface to ensure minimal jitter. Cascaded PLLs are not recommended
for DDR/DDR2 SDRAM interfaces as jitter can accumulate with the use of cascaded
PLLs causing the memory output clock to violate the memory device jitter
specification. Also, ensure that the input clock to the PLL is stable before the PLL
locks. If not, you must perform a manual PLL reset and relock the PLL to ensure that
the phase relationship between all PLL outputs are properly set.