Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 123)

June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
7. Latency
Latency is defined using the local (user) side frequency and absolute time (ns). There
are two types of latencies that exists while designing with memory controllers—read
and write latencies, which have the following definitions:
■ Read latency—the amount of time it takes for the read data to appear at the local
interface after initiating the read request.
■ Write latency—the amount of time it takes for the write data to appear at the
memory interface after initiating the write request.
1 For a half-rate controller, the local side frequency is half of the memory interface
frequency. For a full-rate controller, the local side frequency is equal to the memory
interface frequency.
Altera defines read and write latencies in terms of the local interface clock frequency
and by the absolute time for the memory controllers. These latencies apply to
supported device families (
Table 1–1 on page 1–2 ) with the following memory
controllers:
■ Half-rate HPC II
■ Full-rate HPC II
The latency defined in this section uses the following assumptions:
■ The row is already open, there is no extra bank management needed.
■ The controller is idle, there is no queued transaction pending, indicated by the
local_ready
signal asserted high.
■ No refresh cycles occur before the transaction.