Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 49)

Chapter 5: Functional Description—ALTMEMPHY 5–3
Block Description
June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
Calibration
The sequencer performs calibration to find the optimal clock phase for the memory
interface.
f For information about calibration, refer to Chapter 3 of the Debugging section in
volume 4 of the External Memory Interface Handbook.
Address and Command Datapath
This topic describes the address and command datapath.
Arria GX, Arria II GX, Cyclone III, HardCopy II, Stratix II, and Stratix II GX
Devices
The address and command datapath for full-rate designs is similar to half-rate
designs, except that the address and command signals are all asserted for one
memory clock cycle only (1T signaling).
The address and command datapath is responsible for taking the address and
command outputs from the controller and converting them from half-rate clock to
full-rate clock. Two types of addressing are possible:
■ 1T (full rate)—the duration of the address and command is a single memory clock
cycle (mem_clk_2x,
Figure 5–2 ). This applies to all address and command signals in
full-rate designs or mem_cs_n, mem_cke, and mem_odt signals in half-rate designs.
■ 2T (half rate)—the duration of the address and command is two memory clock
cycles. For half-rate designs, the ALTMEMPHY megafunction supports only a
burst size of four, which means the burst size on the local interface is always set to
1
. The size of the data is 4n-bits wide on the local side and is n-bits wide on the
memory side. To transfer all the 4n-bits at the double data rate, two memory-clock
cycles are required. The new address and command can be issued to memory
every two clock cycles. This scheme applies to all address and command signals,
except for mem_cs_n, mem_cke, and mem_odt signals in half-rate mode.
1 Refer to Table 5–4 in “PLL” on page 5–5 to see the frequency relationship of
mem_clk_2x with the rest of the clocks.