Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 36)

3–10 Chapter 3: Parameter Settings
ALTMEMPHY Parameter Settings
External Memory Interface Handbook Volume 3 June 2011 Altera Corporation
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
For a 2V/ns DQ slew rate rising signal and 2V/ns DQS-DQSn slew rate:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 25 + 100 + 100 =
225 ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 100 + 45 + 62.5 =
207.5 ps
For a 0.5V/ns DQ slew rate rising signal and 1V/ns DQS-DQSn slew rate:
t
DS
(V
REF
) = Base t
DS
+ delta t
DS
+ (V
IH
(ac) – V
REF
)/slew_rate = 25 + 0 + 400 =
425 ps
t
DH
(V
REF
) = Base t
DH
+ delta t
DH
+ (V
IH
(dc) – V
REF
)/slew_rate = 100 – 65 + 250 =
285 ps
A similar approach can be taken to address/command slew rate derating. For t
IS/
t
IH
the slew rate used in the derating equations is the address/command slew rate; for
t
DS/
t
DH
the DQ slew rate is used.
PHY Settings
Click Next or the PHY Settings tab to set the options described in Table 3–6 . The
options are available if they apply to the target Altera device.
Table 3–6. ALTMEMPHY PHY Settings (Part 1 of 2)
Parameter Name Applicable Device Families Description
Use dedicated PLL
outputs to drive
memory clocks HardCopy II and Stratix II
(prototyping for
HardCopy II)
Turn on to use dedicated PLL outputs to generate the external
memory clocks, which is required for HardCopy II ASICs and their
Stratix II FPGA prototypes. When turned off, the DDIO output
registers generate the clock outputs.
When you use the DDIO output registers for the memory clock,
both the memory clock and the DQS signals are well aligned and
easily meets the t
DQSS
specification. However, when the dedicated
clock outputs are for the memory clock, the memory clock and the
DQS signals are not aligned properly and requires a positive phase
offset from the PLL to align the signals together.
Dedicated memory
clock phase
HardCopy II and Stratix II
(prototyping for
HardCopy II) The required phase shift to align the CK/CK# signals with
DQS/DQS# signals when using dedicated PLL outputs to drive
memory clocks.
Use differential DQS
Arria II GX, Stratix III, and
Stratix IV
Enable this feature for better signal integrity. Recommended for
operation at 333 MHz or higher. An option for DDR2 SDRAM only,
as DDR SDRAM does not support differential DQSS.
Enable external access
to reconfigure PLL
prior to calibration
HardCopy II, Stratix II,
Stratix III, and Stratix IV
(prototyping for
HardCopy II)
When enabling this option for HardCopy II, Stratix II, Stratix III, and
Stratix IV devices, the inputs to the ALTPLL_RECONFIG
megafunction are brought to the top level for debugging purposes.
This option allows you to reconfigure the PLL before calibration to
adjust, if necessary, the phase of the memory clock (mem_clk_2x)
before the start of the calibration of the resynchronization clock on
the read side. The calibration of the resynchronization clock on the
read side depends on the phase of the memory clock on the write
side.