DSP56301 User’s Manual
xi
Figures
1-1
DSP56301 Block Diagram ................................................................................... 1-11
2-1
Signals Identified by Functional Group ................................................................. 2-2
2-2
Host Interface/Port B Detail Signal Diagram......................................................... 2-3
3-1
Default Settings (0, 0, 0)......................................................................................... 3-7
3-2
16-Bit Space With Default RAM (0, 0, 1).............................................................. 3-8
3-3
Switched Program RAM (0, 1, 0)........................................................................... 3-9
3-4
16-Bit Space With Switched Program RAM (0, 1, 1).......................................... 3-10
3-5
Instruction Cache Enabled (1, 0, 0) ...................................................................... 3-11
3-6
16-Bit Space With Instruction Cache Enabled (1, 0, 1) ....................................... 3-12
3-7
Switched Program RAM and Instruction Cache Enabled (1, 1, 0) ...................... 3-13
3-8
16-Bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) ..... 3-14
4-1
Status Register (SR) ............................................................................................... 4-7
4-2
Operating Mode Register (OMR)......................................................................... 4-12
4-4
Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE).............................. 4-16
4-3
Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)........................................ 4-16
4-5
PLL Control Register (PCTL) .............................................................................. 4-21
4-6
Bus Control Register (BCR)................................................................................. 4-22
4-7
DRAM Control Register (DCR)........................................................................... 4-24
4-8
Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6) ..................... 4-27
4-9
DMA Control Register (DCR) ............................................................................. 4-29
4-10
Identification Register Configuration (Revision E) ............................................. 4-34
4-11
JTAG Identification (ID) Register Configuration ................................................ 4-35
5-1
Memory Mapping of Peripherals Control Registers .............................................. 5-2
5-2
Host Interface/Port B Detail Signal Diagram......................................................... 5-5
5-3
Port C Signals ......................................................................................................... 5-6
5-4
Port D Signals......................................................................................................... 5-6
5-5
Port E Signals ......................................................................................................... 5-6
5-6
Triple Timer Signals............................................................................................... 5-7
6-1
HI32 Block Diagram .............................................................................................. 6-5
6-2
Connection to a PCI Bus ...................................................................................... 6-19
6-3
Connection to 16-Bit ISA/EISA Data Bus ........................................................... 6-20
6-4
Connection to the DSP56300 Core Port A Bus.................................................... 6-21
6-5
DSP Control Register (DCTR)............................................................................. 6-23
6-6
DSP PCI Control Register (DPCR)...................................................................... 6-26
6-7
DSP PCI Master Control Register (DPMC)......................................................... 6-30