Motorola DSP56301 - Manual (Page 27)

DMA
Overview 1 -11
The block diagram in Figure 1-1 illustrates these buses among other components.
1.6 DMA
The DMA block has the following features:
n Six DMA channels supporting internal and external accesses
n One-, two-, and three-dimensional transfers (including circular buffering)
n End-of-block-transfer interrupts
n Triggering from interrupt lines and all peripherals
Figure 1-1. DSP56301 Block Diagram
PLL
OnCE™
Clock
Generator
Internal
Data
Bus
Switch
Program RAM
4096
×
24
(Default)
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODC/ IRQB
MODB/ IRQC
External
Data Bus
Switch
14
MODA/ IRQD
DSP56300
6 52
24-Bit
24
24
X Data
RAM
2048
×
24
(Default)
Y Data
RAM
2048
×
24
(Default)
DDB
DAB
Memory Expansion Area
Peripheral
Core
YM
_EB
XM
_EB
PM
_
E
B
PIO_EB
Expansion Area
6
SCI
JTAG
3
RESET
MODD/ IRQA
PINIT/ NMI
2
Boot-
strap
ROM
EXTAL
XTAL
ADDRESS
CONTROL
DATA
Triple
Timer
Host
Interface
(HI32)
ESSI
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56
→
56-bit
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I - Cache
Control
External
Address
Bus
Switch
5
DE
MAC