Motorola DSP56301 User Manual
Page 163
Host-Side Programming Model
Host Interface (HI32)
6
-45
hardware can be used with the handshake flags to transfer data without host processor
intervention.
n
When a host bus is less than 24 bits wide, the unused data pins must be forced or pulled
up or down to V
CC
or to GND, respectively. For example, for a 16-bit bus (such as an
ISA bus), HP[48–41] must be forced or pulled up to V
CC
or pulled down to GND.
In PCI mode:
n
In memory space read/write transactions, the HI32 occupies 16384 Dwords. The host
can access the HTXR FIFO and HRXS FIFO at 16377 Dword locations. These FIFOs
appear to the external host as 16377 Dwords of read/write memory. Registers are
accessed as 32-bit data words.
n
The
HAD[1–0]
pins should be zero during the address phase of a transaction. The HI32
responds with a target-disconnect transaction termination with the first data phase if
HAD[1–0]
≠
$0 during the address phase.
n
Configuration space accesses:
— In read/write transactions, the HI32 occupies 64 Dwords. The configuration
registers are accessed as 32-bit Dwords, so the
HAD[1–0]
pins must be zero during
the address phase. The HI32 ignores the transaction if
HAD[1–0]
≠
$0 during the
address phase of a configuration transaction.
— In HCTR, HSTR, HCVR, and configuration space register accesses, if all four byte
lanes are disabled, the HI32 completes the data phase without affecting any flags or
data.
n
PCI host-to-DSP data transfers:
— In transfers to the HI32 registers (HCTR, HSTR, HCVR, and all configuration
space registers), disabled byte lanes (that is, the corresponding byte enable line is
deasserted) are not written and the corresponding bytes do not contain significant
data.
— Data is written to the HTXR FIFO in accordance with FC[1– 0] or HTF[1–0] bits,
regardless of the value of the byte enable pins (
HC3
/
HBE3
–
HC0
/
HBE0
).
n
In PCI DSP-to-host data transfers via the HRXS or HRXM, all four byte lanes are
driven with data, in accordance with FC[1–0] or HRF[1–0] bits, regardless of the value
of the byte enable pins (
HC3
/
HBE3
-
HC0
/
HBE0
).
n
In HI32-to-PCI agent data transfers, all four byte lanes are driven with data, regardless
of the value of the byte enables. As a PCI target, the HI32 executes the PCI bus
command as shown in Table 6-18.