Motorola DSP56301 - Manual (Page 34)

Power
2 -4 DSP56301 User’s Manual
2.1 Power
2.2 Ground
Table 2-2. Power Inputs
Power
Name
Description
V
CCP
PLL Power—V
CC
dedicated for PLL use. The voltage should be well-regulated and the input should be provided
with an extremely low impedance path to the V
CC
power rail.
V
CCQL
Quiet Core (Low) Power—An isolated power for the core processing logic. This input must be isolated
externally from all other chip power inputs. The user must provide adequate external decoupling capacitors.
V
CCQH
Quiet External (High) Power—A quiet power source for I/O lines. This input must be tied externally to all other
chip power inputs. The user must provide adequate decoupling capacitors.
V
CCA
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input must be tied
externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
V
CCD
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied externally
to all other chip power inputs. The user must provide adequate external decoupling capacitors.
V
CCC
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied externally to all
other chip power inputs. The user must provide adequate external decoupling capacitors.
V
CCH
Host Power—An isolated power for the HI32 I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling capacitors.
V
CCS
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input must be
tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors.
Table 2-3. Ground Signals
Ground
Name
Description
GND
P
PLL Ground— GND dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground. V
CCP
should be bypassed to GND
P
by a 0.47
µ
F capacitor located as close as
possible to the chip package.
GND
P1
PLL Ground 1—GND dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground.
GND
Q
Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied externally to
all other chip ground connections. The user must provide adequate external decoupling capacitors.
GND
A
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This connection must be
tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
GND
D
Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GND
N
Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling capacitors.
GND
H
Host Ground—An isolated ground for the HI32 I/O drivers. This connection must be tied externally to all other
chip ground connections. The user must provide adequate external decoupling capacitors.
GND
S
ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This connection
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors.