Motorola DSP56301 - Manual (Page 16)

xvi DSP56301 User’s Manual
6-10 DSP Control Register (DCTR) Bit Definitions ....................................................... 6-23
6-11 DSP PCI Control Register (DPCR) Bit Definitions ................................................ 6-27
6-12 DSP PCI Master Control Register (DMPC) Bit Definitions ................................... 6-31
6-13 DSP PCI Address Register (DPAR) Bit Definitions ............................................... 6-33
6-14 DSP Status Register (DSR) Bit Definitions............................................................. 6-35
6-15 DSP PCI Status Register (DPSR) Bit Definitions ................................................... 6-38
6-16 DATH and DIRH Functionality .............................................................................. 6-43
6-17 HI32 Programming Model, Host-Side Registers ..................................................... 6-44
6-18 PCI Bus Commands................................................................................................. 6-46
6-19 Host-Side Registers (PCI Memory Address Space
1
)............................................... 6-47
6-20 Host-Side Registers (PCI Configuration Address Space
1
) ...................................... 6-47
6-21 Host-Side Registers (Universal Bus Mode Address Space
1
)................................... 6-47
6-22 Host Interface Control Register (HCTR) Bit Definitions ........................................ 6-49
6-23 Host Interface Status Register (HSTR) Bit Definitions........................................... 6-57
6-24 Host Command Vector Register (HCVR) Bit Definitions ...................................... 6-60
6-25 Device ID/Vendor ID Configuration Register (CDID/CVID) Bit Definitions........ 6-64
6-26 Status/Command Configuration Register (CSTR/CCMR) Bit Definitions ............. 6-65
6-27 Class Code/Revision ID Configuration Register (CCCR/CRID) Bit Definitions ... 6-67
6-28 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)
Bit Definitions.......................................................................................................... 6-68
6-29 Memory Space Base Address Configuration Register (CBMA) Bit Definitions .... 6-70
6-30 Interrupt Line-Interrupt Pin Configuration Register(CILP) Bit Definitions .......... 6-73
7-1 ESSI Clock Sources ................................................................................................... 7-3
7-2 Mode and Signal Definitions ..................................................................................... 7-5
7-3 ESSI Control Register A (CRA) Bit Definitions ..................................................... 7-15
7-4 ESSI Control Register B (CRB) Bit Definitions ..................................................... 7-19
7-5 ESSI Status Register (SSISR) Bit Definitions ......................................................... 7-28
7-6 ESSI Port Signal Configurations ............................................................................. 7-37
8-1 SCI Registers After Reset .......................................................................................... 8-5
8-2 SCI Control Register (SCR) Bit Definitions............................................................ 8-12
8-3 SCI Status Register .................................................................................................. 8-17
8-4 SCI Status Register (SSR) Bit Definitions .............................................................. 8-17
8-5 SCI Clock Control Register (SCCR) Bit Definitions .............................................. 8-19
9-1 Timer Prescaler Load Register (TPLR) Bit Definitions .......................................... 9-27
9-2 Timer Prescaler Count Register (TPCR) Bit Definitions ........................................ 9-28
9-3 Timer Control/Status Register (TCSR) Bit Definitions........................................... 9-28
9-4 Inverter (INV) Bit Operation ................................................................................... 9-32
B-1 Guide to Programming Sheets ...................................................................................B-2
B-2 Internal I/O Memory Map (X Data Memory)............................................................B-3
B-3 Interrupt Sources........................................................................................................B-9
B-4 Interrupt Source Priorities Within an IPL................................................................B-11