Motorola DSP56301 - Manual (Page 371)

Index -15
Timer Overflow Interrupt Enable (TOIE) 9-32
Timer Reload Mode (TRM) 9-30
Timer Count Register (TCR) 9-34
Timer Load Registers (TLR) 9-33
Timer Prescaler Count Register (TPCR) 9-28
Prescaler Counter Value (PC) 9-28
Timer Prescaler Load Register (TPLR) 9-27
bit definitions 9-27
Prescaler Preload Value (PL) 9-27
Prescaler Source (PS) 9-27
Timer Compare Flag (TCF) bit 9-29
Timer Compare Interrupt Enable (TCIE) bit 9-32
Timer Compare Register (TCPR) 9-4
, 9-34
Timer Control (TC) bits 9-31
Timer Control/Status Register (TCSR) 9-3
, 9-28
bit definitions 9-28
Data Input (DI) 9-29
Data Output (DO) 9-29
Direction (DIR) 9-30
Inverter (INV) 9-30
, 9-32
Prescaler Clock Enable (PCE) 9-29
programming sheet B-38
Timer Compare Flag (TCF) 9-29
Timer Compare Interrupt Enable (TCIE) 9-32
Timer Control (TC) 9-31
Timer Enable (TE) 9-32
Timer Overflow Flag (TOF) 9-29
Timer Overflow Interrupt Enable (TOIE) 9-32
Timer Reload Mode (TRM) 9-30
Timer Count Register (TCR) 9-34
Timer Enable (TE) bit 9-32
Timer Interrupt Enable (TMIE) bit 8-13
Timer Interrupt Priority Level (TOL) bits 4-16
Timer Interrupt Rate (STIR) bit 8-12
Timer Load Registers (TLR) 9-4
, 9-33
programming sheet B-39
Timer module 1-13
architecture 9-1
timer block diagram 9-2
Timer Overflow Flag (TOF) bit 9-29
Timer Overflow Interrupt Enable (TOIE) bit 9-32
Timer Prescaler Count Register (TPCR) 9-28
bit definitions 9-28
Prescaler Counter Value (PC) 9-28
Timer Prescaler Load Register (TPLR) 9-4 , 9-27
bit definitions 9-27
Prescaler Preload Value (PL) 9-27
Prescaler Source (PS) 9-27
programming sheet B-37
Timer Reload Mode (TRM) bit 9-30
Timers 2-2
Transaction Abort Interrupt Enable (TAIE) bit 6-29
Transaction Termination Interrupt Enable (TTIE) bit 6-29
Transfer Acknowledge (
TA ) 2-7
Transfer Complete Interrupt Enable (TCIE) bit 6-29
Transmit 0 Enable (TE0) bit 7-20
Transmit 1 Enable (TE1) bit 7-21
Transmit 2 Enable (TE2) bit 7-21
Transmit Clock Source (TDM) bit 8-19
Transmit Data Register Empty (TDE) bit 7-28
Transmit Data Register Empty (TDRE) bit 8-18
Transmit Data Registers (TX0–TX2) 7-14
, 7-33
Transmit Data signal ( TXD ) 8-4
Transmit Enable (TE) bits 7-18
Transmit Exception Interrupt Enable (TEIE) bit 7-19
Transmit Frame Sync Flag (TFS) 7-29
Transmit Interrupt Enable (TIE) bit 7-20
Transmit Last Slot Interrupt Enable (TLIE) bit 7-19
Transmit Request Enable (TREQ) bit 6-56
Transmit Shift Registers 7-30
Transmit Slot Mask Registers (TSMA and TSMB) 7-14
,
7-33
Transmitter Empty (TRNE) bit 8-18
Transmitter Enable (TE) bit 8-14
Transmitter Ready (TRDY) bit 6-58
Transmitter Underrun Error Flag (TUE) 7-28
triple timer module 1-13
TX clock 7-11
TXD signal 8-4
U
Universal Bus
modes 6-44 , 6-63
Universal Bus mode 6-15 , 6-63
16-bit 6-48 , 6-57 , 6-63
24-bit 6-56
Universal Bus Mode Address Space 6-47
Universal Bus Mode Base Address (GB[10–3]) bits 6-70
Universal Host Interface 1-5
Unnormalized (U) bit 4-11
V
VBA register 1-8
Vector Base Address register (VBA) 1-8
W
Wait Cycle Control (WCC) bit 6-66
Wakeup Mode Select (WAKE) bit 8-15
Wired-OR Mode Select (WOMS) bit 8-14
Word Length Control (WL) bits 7-15
Word Select (WDS) bits 8-16
Write (
WR ) 2-7
X
X data memory 3-3