Motorola DSP56301 - Manual (Page 281)

Operating Modes
Triple Timer Module 9 -19
9.3.3 Pulse Width Modulation (PWM, Mode 7)
In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the
value in the TCPR, the
TIO output signal is toggled and TCSR[TCF] is set. The contents of the
counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare interrupt is
generated. The counter continues to increment on each timer clock.
If counter overflow occurs, the TIO output signal is toggled, TCSR[TOF] is set, and an
overflow interrupt is generated if the TCSR[TOIE] bit is set. If the TCSR[TRM] bit is set, the
counter is loaded with the TLR value on the next timer clock and the count resumes. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
When the TCSR[TE] bit is set and the counter starts, the TIO signal assumes the value of INV.
On each subsequent toggle of the TIO signal, the polarity of the TIO signal is reversed. For
example, if the INV bit is set, the TIO signal generates the following signal: 1010. If the INV
bit is cleared, the TIO signal generates the following signal: 0101.
The value of the TLR determines the output period ($FFFFFF
−
TLR + 1). The timer counter
increments the initial TLR value and toggles the TIO signal when the counter value exceeds
$FFFFFF. The duty cycle of the TIO signal is determined by the value in the TCPR. When the
value in the TLR increments to a value equal to the value in the TCPR, the TIO signal is
toggled. The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF
−
TLR + 1). For
a 50 percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2.
Note: The value in TCPR must be greater than the value in TLR.
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 1 1 7 Pulse width modulation PWM Output Internal