Motorola DSP56301 - Manual (Page 365)

Index -9
I
I/O space
X data memory 3-4
Y data memory 3-5
Idle Line Flag (IDLE) bit 8-18
Idle Line Interrupt Enable (ILIE) bit 8-13
Idle Line Wakeup mode 8-3
illegal PCI events 6-46
initialization
system 5-1
initializing the timer 9-3
input data alignment 6-3
Insert Address Enable (IAE) bit 6-27
instruction cache 1-5
, 3-2
location 3-6
instruction cache controller 1-4
internal buses 1-10
internal memory configuration summary 3-6
internal program memory 3-1
, 3-2
interrupt 1-8
configuring 4-15
source priorities 4-19
sources 4-16
, 4-17
table 4-15
table, memory map 4-17
trigger mode 4-17
vector 4-17
interrupt and mode control 2-1 , 2-9
interrupt control 2-9
Interrupt Line (IL[7–0]) bits 6-73
Interrupt Line-Interrupt Pin Configuration Register
(CILP)
Interrupt Line (IL[7–0]) 6-73
Interrupt Pin (IP[7–0]) 6-73
MAX_LAT (ML[7–0]) 6-73
MIN_GNT (MG[7–0]) 6-73
Interrupt Mask (I) bits 4-10
Interrupt Pin (IP[7–0]) bits 6-73
Interrupt Priority Register Core (IPRC) 4-16
IRQD – IRQA Priority and Mode (IDL–IAL) 4-16
programming sheet B-15
Interrupt Priority Register Peripherals (IPRP) 4-16
ESSI0 Interrupt Priority Level (S0L) 4-16
ESSI1 Interrupt Priority Level (S1L) 4-16
HI32 Interrupt Priority Level (HPL) 4-16
programming sheet B-16
SCI Interrupt Priority Level (SCL) 4-16
Timer Interrupt Priority Level (TOL) 4-16
Interrupt Request A ( IRQA ) 2-9
Interrupt Request B ( IRQB ) 2-9
Interrupt Request C( IRQC ) 2-9
Interrupt Request D ( IRQD ) 2-9
Interrupt Service Routine (ISR) 7-9 , 9-4
interrupt trigger event 7-9
interrupts 1-4
, 5-2 , 5-3
core
HI32 6-4
Inverter (INV) bit 9-30 , 9-32
IRQD – IRQA Priority and Mode (IDL–IAL) bits 4-16
ISA/EISA bus DMA-type accesses 6-15
J
Joint Test Action Group (JTAG) 1-5 , 1-9 , 4-35
interface 2-29
JTAG/OnCE Port 2-2
L
Latency Timer (High) (LT[7–0]) 6-69
Limit (L) bit 4-11
Literature Distribution Center 1-14
Loop Address (LA) register 1-8
Loop Counter (LC) register 1-8
low-power state 6-13
M
M68HC11 SCI interface 8-16
MA–MD bits 4-5
mapping control registers 5-2
Master Access Counter Enable (MACE) 6-28
Master Address Interrupt Enable (MAIE) bit 6-30
Master Data Transferred (MDT) bit 6-39
Master Receive Interrupt Enable (MRIE) bit 6-30
Master Transfer Terminate (MTT) bit 6-28
Master Transmit Interrupt Enable (MTIE) bit 6-30
Master Wait State Disable (MWSD) bit 6-28
MAX_LAT (ML[7–0]) bits 6-73
MC68681 DUART 8-16
memory
allocation switching 3-2
configuration 3-5
configuration summary 3-6
dynamic switching 3-5
expansion 3-1
maps 3-7
on-chip 1-10
Memory Base Address High/Low (PM[31–16]) bits 6-70
Memory Base Address Low (PM[15–4]) 6-71
memory expansion port 1-5
memory space
X I/O 5-2
Memory Space (MS[1–0]) bits 6-71
Memory Space Base Address Configuration Register
(CBMA)
Memory Base Address High/Low (PM[31–16] 6-70