Motorola DSP56301 - Manual (Page 368)

Index -12 DSP56301 User’s Manual
Receive Slot Mask Registers (RSMA and RSMB) 7-14 ,
7-35
Receive with Exception Interrupt Enable (REIE) bit 8-12
Received Bit 8 (R8) bit 8-17
Received Master Abort (RMA) bit 6-65
Received Target Abort (RTA) 6-65
Receiver Enable (RE) bit 8-14
Receiver Overrun Error Flag (ROE) 7-28
Receiver Wakeup Enable (RWU) bit 8-15
Related Documents and Web Sites 1-14
Remaining Data Count (RDC[5–0]) bits 6-38
Remaining Data Count Qualifier (RDCQ) bit 6-38
RESET 2-9
reset
STOP 6-12
reset state 4-2 , 4-5
HI32 6-12
reverse-carry adder 1-7
Revision ID (RID[7–0]) bits 6-67
ROM, bootstrap 3-1
, 3-3
Rounding Mode (RM) bit 4-7
RX clock 7-11
S
SC register 1-8
Scaling (S) bit 4-10
Scaling (S) Mode bits 4-10
SCI Clock Control Register (SCCR) 8-9
, 8-19
bit definitions 8-19
Clock Divider (CD) 8-20
Clock Out Divider (COD) 8-19
Clock Prescaler (SCP) 8-19
programming sheet B-36
Receive Clock Mode Source (RCM) 8-19
Transmit Clock Source (TCM) 8-19
SCI Clock Polarity (SCKP) bit 8-12
SCI Control Register (SCR) 8-9
, 8-12
bit definitions 8-12
Idle Line Interrupt Enable (ILIE) 8-13
programming sheet B-35
Receive with Exception Interrupt Enable (REIE) 8-12
Receiver Enable (RE) 8-14
Receiver Wakeup Enable (RWU) 8-15
SCI Clock Polarity (SCKP) 8-12
SCI Receive Interrupt Enable (RIE) 8-13
SCI Shift Direction (SSFTD) 8-15
SCI Transmit Interrupt Enable (TIE) 8-13
Send Break (SBK) 8-15
Timer Interrupt Enable (TMIE) 8-13
Timer Interrupt Rate (STIR) 8-12
Transmitter Enable (TE) 8-14
Wakeup Mode Select (WAKE) 8-15
Wired-OR Mode Select (WOMS) 8-14
Word Select (WDS) 8-16
SCI Interrupt Priority Level (SCL) bits 4-16
SCI Receive Data Register (SRX) 8-9
, 8-22
SCI Receive Interrupt Enable (RIE) bit 8-13
SCI Serial Clock signal (
SCLK ) 8-4
SCI Shift Direction (SSFTD) 8-15
SCI Status Register (SSR) 8-9
, 8-17
bit definitions 8-17
Framing Error Flag (FE) 8-17
Idle Line Flag (IDLE) 8-18
Overrun Error Flag (OR) 8-18
Parity Error (PE) 8-17
Receive Data Register Full (RDRF) 8-18
Received Bit 8 (R8) 8-17
Transmit Data Register Empty (TDRE) 8-18
Transmitter Empty (TRNE) 8-18
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Register (STX or STXA) 8-22
SCI Transmit Data Register (STX) 8-9
, 8-23
SCI Transmit Interrupt Enable (TIE) bit 8-13
SCLK 8-2 , 8-6
SCS byte 4-12
Select SCK (SSC1) bit 7-15
Self-Configuration mode 6-12
, 6-44 , 6-72
Send Break (SBK) bit 8-15
Serial Clock (
SCK ) 7-3
Serial Clock ( SCLK ), SCI 8-2
Serial Communications Interface (SCI) 1-5 , 1-6 , 1-13 ,
2-2 , 8-1
Address Mode Wakeup 8-3
Asynchronous mode 8-2
bootstrap loading 8-8
crystal frequency 8-6
data registers 8-22
Data Word Formats 8-10
enable wakeup function 8-15
enable/disable SCI receive data with exception
interrupt 8-12
exceptions 8-8
Idle Line 8-9
Receive Data 8-8
Receive Data with Exception Status 8-8
Timer 8-9
Transmit Data 8-8
GPIO 5-6
GPIO functionality 8-24
I/O signals 8-3
Idle Line Wakeup mode 8-3
individual reset state (PCR = $0) 8-6
initialization 8-6
Inter-processor messages 8-2
interrupts 8-6
Multidrop mode 8-2
operating mode 8-1