Motorola DSP56301 User Manual
Page 207
Operation
Enhanced Synchronous Serial Interface (ESSI)
7
-9
To configure an ESSI exception, perform the following steps:
1.
Configure the interrupt service routine (ISR):
a.
Load vector base address register
VBA (b23:8)
b.
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c.
Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
p:I_SI0TD
2.
Configure interrupt trigger; preload transmit data
a.
Enable and prioritize overall peripheral interrupt functionality.
IPRP (S0L1:0)
b.
Write data to all enabled transmit registers.
TX00
c.
Enable a peripheral interrupt-generating function.
CRB (TE0)
d.
Enable a specific peripheral interrupt.
CRB0 (TIE)
e.
Enable peripheral and associated signals.
PCRC (PC[5–0])
f.
Unmask interrupts at the global level.
SR (I1–0)
Note:
The example material to the right of the steps shows register settings for
configuring an ESSI0 transmit interrupt using transmitter 0. The order of the steps
is optional except that the interrupt trigger configuration must not be completed
until the ISR configuration is complete. Since step 2c may cause an immediate
transmit without generating an interrupt, perform the transmit data preload in
step 2b before step 2c to ensure that valid data is sent in the first transmission.
After the first transmit, subsequent transmit values are typically loaded into TXnn
by the ISR (one value per register per interrupt). Therefore, if N items are to be sent
from a particular TXnn, the ISR needs to load the transmit register (N – 1) times.
Steps 2c and 2d can be performed in step 2a as a single instruction. If an interrupt
trigger event occurs before all interrupt trigger configuration steps are performed,
the event is ignored and not queued. If interrupts derived from the core or other
peripherals need to be enabled at the same time as ESSI interrupts, step 2f should
be performed last.