Motorola DSP56301 - Manual (Page 77)

Operating Modes
Core Configuration 4 -3
Table 4-2. Operating Mode Definitions
Mode Description
0 Expanded mode—Bypasses the bootstrap ROM. The DSP56301 begins fetching instructions, starting at
$C00000. Memory accesses are performed using SRAM memory access type with 31 wait states and no
address attributes selected (default).
1 Bootstrap from byte-wide memory—Loads a program memory segment from consecutive byte-wide P
memory locations, starting at P:$D00000 (bits 7-0). The memory is selected by the Address Attribute AA1
and is accessed with 31 wait states. The EPROM bootstrap code expects first to read 3 bytes specifying
the number of program words, then 3 bytes specifying the address to start loading the program words,
and then 3 bytes for each program word to be loaded. The number of words, the starting address, and the
program words are read least significant byte first followed by the middle and then the most significant
byte. The program concatenates consecutive three byte sequences into 24-bit words and stores them in
contiguous PRAM memory locations starting at the specified address. After the program words are read,
program execution starts from the same address where loading started.
2 Bootstrap through SCI—The hardware reset vector is located at address $FF0000 in the bootstrap
ROM. The program bootstraps through the SCI. The bootstrap program sets the SCI to operate in 10-bit
asynchronous mode, with 1 start bit, 8 data bits, 1 stop bit, and no parity. Data is received in this order:
start bit, 8 data bits (LSB first), and one stop bit. Data is aligned in the SCI receive data register with the
LSB of the least significant byte of the received data appearing at Bit 0.The user must provide an external
clock source with a frequency at least 16 times the transmission data rate. Each byte received by the SCI
is echoed back through the SCI transmitter to the external transmitter. The boot program concatenates
every three bytes read from the SCI into a 24-bit wide DSP56301 word.
Note: DSP CLKOUT rate must be at least 64 times the data transmission rate.
3 Host bootstrap in DSP-to-DSP mode—The hardware reset vector is located at address $FF0000 in the
bootstrap ROM. The program bootstraps through the HI32 in UB mode, double strobe, HTA pin active
low. The DSP56301 is written with 24-bit-wide words.
Note: DSP CLKOUT rate must be at least three times the data transfer rate.
4 Bootstrap from SPI-compatible Serial EEPROM through the SCI—The hardware reset vector is at
address $FF0000 in the bootstrap ROM. The program bootstraps through the HI32 in standard PCI slave
configuration. The DSP56301 is written with 24-bit-wide words encapsulated in 32-bit wide PCI transfers.
Note: DSP CLKOUT rate must be 5/3 of the PCI clock.
5 Host bootstrap 16-bit wide ISA slave glueless interface in UB mode—Loads the program memory
from the Host Interface programmed to operate in the Universal Bus mode supporting ISA (slave)
glueless connection. Using Self-Configuration mode, the base address in the CBMA is initially written with
$2F, corresponding to an ISA HTXR address of $2FE (Serial Port 2 Modem Status read-only register).
The HI32 bootstrap code expects to read 32 consecutive times the
magic number $0037. Subsequently,
the bootstrap code expects to read a 16-bit word that is the designated ISA Port Address; this address is
written into the CBMA. The HOST Processor must poll for the Host Interface to be reconfigured. This
must be done by reading the HSTR and verifying that the value $0013 is read. Then the host processor
starts writing data to the Host Interface. The HI32 bootstrap code expects to read a 24-bit word first that
specifies the number of program words, followed by a 24-bit word specifying the address from which to
start loading the program words, followed by a 24-bit word for each program word to be loaded. The
program words are stored in contiguous PRAM memory beginning at the specified starting address. After
reading the program words, program execution starts from the address where loading started.
Note: DSP CLKOUT rate must be at least three times the data transfer rate.