Motorola DSP56301 - Manual (Page 364)

Index -8 DSP56301 User’s Manual
initializing configuration registers 6-4
input and output data transfers 6-4
interrupt 6-22
Interrupt Line-Interrupt Pin Configuration Register
(CILP) 6-73
Interrupt Line (IL[7–0]) 6-73
Interrupt Pin (IP[7–0]) 6-73
MAX_LAT (ML[7–0] 6-73
MIN_GNT (MG[7–0]) 6-73
interrupt requests 6-4
low power state 6-13
Memory Space Base Address Configuration Register
(CBMA) 6-70
Memory Base Address High/Low
(PM[31–16]) 6-70
Memory Base Address Low (PM[15–4]) 6-71
Memory Space (MS[1–0]) 6-71
Memory Space Indicator (MSI) 6-71
Pre-Fetch (PF) 6-71
Universal Bus Mode Base Address
(GB[10–3]) 6-70
memory space read/write transactions 6-45
Memory Write and Invalidate command 6-34
memory-to-HI32 data transfers 6-22
modes 6-13
MOVE instruction 6-42
MOVEP instruction 6-22
NMIs 6-6
operating modes 6-12
, 6-18
parity 6-4
PCI configuration registers 6-44
PCI DSP-to-host transaction 6-31
PCI host-to-DSP data transfers 6-45
PCI host-to-DSP transaction 6-31
PCI idle state 6-13
PCI master data transfer formats 6-8
PCI master transaction termination 6-28
PCI mode 2-2
, 6-13 , 6-45 , 6-63
PCI target data transfers 6-6 , 6-7
personal software reset state 6-12 , 6-13
pin functionality 6-18
pins 6-16
preventing data overwriting 6-42
reset 6-12
reset states 6-12
Self-Configuration mode 6-44
, 6-72
signalling environments 6-4
signals 2-1
, 2-10
signals and modes 2-14
software mastership arbitration 6-49
software-driven PCI Interrupt Requests 6-4
standard polling 6-22
Status/Command Configuration Register
(CSTR/CCMR) 6-64
Data Parity Reported (DPR) 6-65
Detected Parity Error (DPE) 6-65
DEVSEL Timing (DST[1–0]) 6-65
Fast Back-to-Back Capable (FBBC) 6-66
Memory Space Enable (MSE) 6-66
Parity Error Response (PERR) 6-66
PCI Bus Master Enable (BM) 6-66
Received Master Abort (RMA) 6-65
Received Target Abort (RTA) 6-65
Signaled System Error (SSE) 6-65
Signalled Target Abort (STA) 6-65
System Error Enable (SERE) 6-66
Wait Cycle Control (WCC) 6-66
STOP reset 6-12
Subsystem ID and Subsystem Vendor ID
Configuration Register (CSID) 6-71
system errors 6-4
target-disconnect-C/retry event 6-13
terminate and reset 6-13
Universal Bus mode 6-15
Universal Bus Mode Address Space 6-47
Universal Bus modes 6-44
, 6-63
vectored DSP56300 core interrupts 6-4
Host Interface Status Register (HSTR) 6-56
Host Flags 5–3 (HF[5–3]) 6-57
Host Interrupt A (HINT) 6-57
Host Receive Data Request (HRRQ) 6-58
Host Request (HREQ) 6-57
Host Transmit Data Request (HTRQ) 6-58
Transmitter Ready (TRDY) 6-58
Host Interrupt A (HINT) bit 6-25 , 6-57
Host Interrupt Request Drive Control (HIRD) bit 6-24
Host Interrupt Request Handshake Mode (HIRH) bit 6-24
Host Master Receive Data Register (HRXM) 6-7
, 6-61
Host Non-Maskable Interrupt (HNMI) bit 6-60
Host Read/Write Polarity (HRWP) bit 6-25
Host Receive Data Request (HRRQ) bit 6-58
Host Receive Data Transfer Format (HRF[1–0]) bits 6-50
Host Request 6-57
Host Request (HREQ) bit 6-57
Host Reset Polarity (HRSP) bit 6-24
Host Semaphores (HS[2–0]) bits 6-49
Host Slave Receive Data Register (HRXS) 6-61
, 6-62
Host Transfer Acknowledge Polarity (HTAP) bit 6-25
Host Transmit Data Register (HTXR) 6-62
Host Transmit Data Request (HTRQ) bit 6-58
Host Transmit Data Transfer Format (HTF[1–0]) bits 6-51
HPERR pin 6-66
HRST / HRST pin 6-12
HSERR Force (SERF) bit 6-28
HSERR pin 6-66