Motorola DSP56301 - Manual (Page 15)

Tables xv
Tables
1-1 High True/Low True Signal Conventions ................................................................. 1-2
1-2 DSP56301 Switch Memory Configuration.............................................................. 1-10
1-3 DSP56301 Documentation ...................................................................................... 1-14
2-1 DSP56301 Functional Signal Groupings ................................................................... 2-1
2-2 Power Inputs .............................................................................................................. 2-4
2-3 Ground Signals .......................................................................................................... 2-4
2-4 Clock Signals ............................................................................................................. 2-5
2-5 Phase-Lock Loop Signals .......................................................................................... 2-5
2-6 External Address Bus Signals.................................................................................... 2-6
2-7 External Data Bus Signals ......................................................................................... 2-6
2-8 External Bus Control Signals..................................................................................... 2-6
2-9 Interrupt and Mode Control ....................................................................................... 2-9
2-10 Host Interface........................................................................................................... 2-10
2-11 Summary of HI32 Signals and Modes ..................................................................... 2-14
2-12 Host Port Pins (HI32) .............................................................................................. 2-16
2-13 Enhanced Synchronous Serial Interface 0 ............................................................... 2-23
2-14 Enhanced Serial Synchronous Interface 1 ............................................................... 2-25
2-15 Serial Communication Interface .............................................................................. 2-27
2-16 Triple Timer Signals ................................................................................................ 2-28
2-17 JTAG/OnCE Interface ............................................................................................. 2-29
3-1 DSP56301 RAM Configurations ............................................................................... 3-6
3-2 DSP56301 RAM Address Ranges by Configuration................................................. 3-6
4-1 DSP56301 Operating Modes ..................................................................................... 4-2
4-2 Operating Mode Definitions ...................................................................................... 4-3
4-3 Status Register Bit Definitions ................................................................................. 4-7
4-4 Operating Mode Register (OMR) Bit Definitions ................................................... 4-12
4-5 Interrupt Priority Level Bits..................................................................................... 4-17
4-6 Interrupt Sources...................................................................................................... 4-17
4-7 Interrupt Source Priorities Within an IPL................................................................ 4-19
4-8 PLL Control Register (PCTL) Bit Definitions ........................................................ 4-21
4-9 Bus Control Register (BCR) Bit Definitions ........................................................... 4-22
4-10 DRAM Control Register (DCR) Bit Definitions ..................................................... 4-25
4-11 Address Attribute Registers (AAR[0–3]) Bit Definitions ....................................... 4-27
4-12 DMA Control Register (DCR) Bit Definitions........................................................ 4-29
6-1 HI32 Features, Core-Side and Host-Side................................................................... 6-2
6-2 HI32 Features in PCI Mode and Universal Bus Mode .............................................. 6-3
6-3 HI32 (PCI Master Data Transfer Formats ................................................................. 6-8
6-4 Transmit Data Transfer Format ................................................................................. 6-9
6-5 Receive Transfer Data Formats ............................................................................... 6-10
6-6 HI32 Reset ............................................................................................................... 6-12
6-7 HI32 Modes ............................................................................................................. 6-13
6-8 Host Port Pin Functionality...................................................................................... 6-18
6-9 HI32 Programming Model, DSP Side ..................................................................... 6-22