Motorola DSP56301 - Manual (Page 367)

Index -11
PCI-only registers
DSP PCI Address Register (DPAR) 6-33
DSP PCI Master Control Register (DPMC) 6-30
DSP PCI Port Control Register (DPCR) 6-26
DSP PCI Status Register (DPSR) 6-38
Peripheral Component Interconnect (PCI) 1-5
configuration registers 6-44
illegal events 6-46
PCI Specification Revision 2.0 6-1
Peripheral I/O Expansion Bus 1-10
peripheral programming 5-1
personal software reset state 6-12
HI32 6-12
Phase-Lock Loop (PLL) 2-5
signals 2-1 , 2-5
Phase-Lock Loop (PLL) Initial ( PINIT ) state 2-5
PINIT 4-21
PLL 1-9
PLL Capacitor (
PCAP ) 2-5
PLL Control (PCTL) register 4-21
Clock Output Disable (COD) 4-21
Crystal Range (XTLR) 4-21
Division Factor (DF) 4-21
PLL Enable (PEN) 4-21
PLL Multiplication Factor (MF) 4-21
PLL Stop State (PSTP) 4-21
Predivider Factor (PD) 4-21
programming sheet B-17
XTAL Disable (XTLD) 4-21
PLL Enable (PEN) bit 4-21
PLL Stop State (PSTP) bit 4-21
polling 5-2
Port A 2-6
, 4-22
Port B 5-5
GPIO 2-3 , 5-5
programming sheet B-40
Port C 2-2 , 2-23 , 5-6
control registers 7-36
Port C Control Register (PCRC) 7-36
programming sheet B-41
Port C Data Register (PDRC) 7-38
programming sheet B-41
Port C Direction Register (PRRC) 7-37
programming sheet B-41
Port D 2-2 , 2-25 , 5-6
control registers 7-36
Port D Control Register (PCRD) 7-36
programming sheet B-42
Port D Data Register (PDRD) 7-38
programming sheet B-42
Port D Direction Register (PRRD) 7-37
programming sheet B-42
Port E 2-27 , 5-6
Port E Control Register (PCRE) 8-24
programming sheet B-43
Port E Data Register (PDRE) 8-25
programming sheet B-43
Port E Direction Register (PRRE) 8-25
programming sheet B-43
Position Independent Code (PIC) support 1-4
power 2-1
, 2-4
Predivider Factor (PD) bits 4-21
Pre-Fetch (PF) bit 6-71
prescale divider for ESSI 7-16
Prescale Modulus Select (PM) bits 7-16
Prescaler Clock Enable (PCE) bit 9-29
prescaler counter 9-25
Prescaler Counter Value (PC) bits 9-28
Prescaler Preload Value (PL) bits 9-27
Prescaler Range (PSR) bit 7-16
Prescaler Source (PS) bits 9-27
Program Address Bus (PAB) 1-10
Program Address Generator (PAG) 1-8
Program Control Unit (PCU) 1-4
, 1-8
Program Counter (PC) register 1-8
Program Data Bus (PDB) 1-10
Program Decode Controller (PDC) 1-8
Program Interrupt Controller (PIC) 1-8
program memory 1-5
, 3-2
internal 3-1
program memory expansion 1-5
Program ROM, bootstrap 3-1
programming model
ESSI 7-14
HI32
DSP side 6-22
host side 6-44
SCI 8-9
timer 9-25
programming peripherals 5-1
R
Read ( RD ) 2-7
Read Address Strobe 0–3 ( RAS[0–3] ) 2-6
Receive Buffer Lock Enable (RBLE) bit 6-27
Receive Clock Mode Source (RCM) 8-19
Receive Data (RXD) signal 8-4
Receive Data Register (RX) 7-30
Receive Data Register Full (RDF) bit 7-28
Receive Data Register Full (RDRF) bit 8-18
Receive Enable (RE) bit 7-20
Receive Exception Interrupt Enable (REIE) bit 7-19
Receive Frame Sync Flag (RFS) 7-29
Receive Interrupt Enable (RIE) bit 7-19
Receive Last Slot Interrupt Enable (RLIE) bit 7-19
Receive Request Enable (RREQ) bit 6-55
Receive Shift Register 7-29