Motorola DSP56301 - Manual (Page 133)

DSP-Side Operating Modes
Host Interface (HI32) 6 -15
(pci_cyc + pci_w.s) x multfactor = tot_cyc
1 + 0 x 2 = 2
multfactor = 2 because f_core = 66 MHz and f_pci = 33 MHz.
Since 4 2/3 (HI32) > 2 (core), this dominates, so the answer is
66/2 = 33 Mwords.
2: (DMA transfer internal memory)
DRXR --> (DMA) --> internal X:
( 1 (src) + 1 (dest) + 0 (w.s.) ) = 2 (DMA As fast as HI32)
= > 66 / 2 = 33 Mwords/sec (Max HI32 Rate)
3: (dma transfer external memory)
core cycles (DMA)
-----------------
1 DMA source access
1 external wait state
1 DMA destination access
--
3 total
DRXR --> (DMA) --> external X:
( 1 (src) + 1 (dest) + 1 (w.s.) ) = 3 (DMA slower than HI32)
= > 66 / 3 = 22 Mwords/sec (DMA-constrained)
6.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] =
$3) Bus Modes
In both Universal bus mode and Enhanced Universal Bus mode, the following are true:
n Glueless connection to various external buses (for example, ISA/EISA, DSP56300
core-based DSP Port A bus).
n 24-bit, 16-bit (with data alignment) and 8-bit buses.
n ISA/EISA bus DMA-type accesses.
n HP19, HP31, and HP32 are unused and must be forced or pulled up to V
CC
.
n When the host bus is less than 24 bits wide, the data pins that are not used for
transferring data must be forced or pulled up or down to V
CC
or to GND, respectively.
For example, for a 16-bit bus (ISA bus and so on), HP[48–41] must be forced or pulled
up to V
CC
or pulled down to GND.