Motorola DSP56301 - Manual (Page 61)

Memory Configuration 3 -1
Chapter 3
Memory Configuration
Like all members of the DSP56300 core family, the DSP56301 addresses three sets of
16 M
×
24-bit memory: program, X data, and Y data. Each of these memory spaces includes
both on-chip and external memory (accessed through the external memory interface). The
DSP56301 is extremely flexible because it has several modes to allocate on-chip memory
between the program memory and the two data memory spaces. You can also configure it to
operate in a special sixteen-bit compatibility mode that allows the chip to use DSP56000
object code without any change; this can result in higher performance of existing code for
applications that do not require a larger address space. This section provides detailed
information on each of these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
n Internal program RAM (4 K by default)
n Instruction cache (optional, 1 K) formed from program RAM. When enabled, the
memory addresses used by the internal cache memory are switched to external
memory. The internal memory in this address range switches to cache-only mode and
is not available via direct addressing when cache is enabled. In systems using
Instruction Cache, always enable the cache (CE = 1) before loading code into internal
program memory; this prevents the condition in which code loaded into program
memory before cache is enabled “disappears” after cache is enabled.
n Off-chip memory expansion (optional, as much as 64 K in 16-bit mode or 16 M in
24-bit mode). Refer to the DSP56300 Family Manual, especially Chapter 9, External
Memory Interface (Port A), for details on using the external memory interface to
access external program memory.
n Bootstrap program ROM (3 K
×
24-bit)
Note: Early versions of the DSP56301 used a 192
×
24-bit bootstrap ROM space.
Note: Program memory space at locations $FF00C0–$FFFFFF is reserved and should not
be accessed.