Motorola DSP56301 - Manual (Page 75)

Core Configuration 4 -1
Chapter 4
Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56301. These
configuration details include the following:
n Operating modes
n Bootstrap program
n Central Processor registers
— Status Register (SR)
— Operating Mode Register (OMR)
n Interrupt Priority Registers (IPRC and IPRP)
n PLL Control (PCTL) register
n Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
n DMA Control Registers 5–0 (DCR[5–0])
n Device Identification Register (IDR)
n JTAG Identification (ID) Register
n JTAG Boundary Scan Register (BSR)
For information about specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.