Motorola DSP56301 - Manual (Page 366)

Index -10 DSP56301 User’s Manual
Memory Base Address Low (PM[15–4]) 6-71
Memory Space (MS[1–0]) 6-71
Memory Space Indicator (MSI) 6-71
Pre-Fetch (PF) 6-71
Universal Bus Mode Base Address (GB[10–3]) 6-70
Memory Space Indicator (MSI) 6-71
Memory Switch (MS) bit 3-7
Memory Switch mode 3-2
X data Memory 3-3
Y data memory 3-4
Memory Switch Mode (MS) bit 4-14
MIN_GNT (MG[7–0]) bits 6-73
MODA – MODD pins 4-2 , 8-8
mode control 2-9
Mode Register (MR) 4-7
Do Loop Flag (LF) 4-8
Double-Precision Multiply Mode (DM) 4-9
Interrupt Mask (I) 4-10
Scaling (S) Mode 4-10
Sixteen-bit Compatibility (SC) mode 4-9
Mode Select (MOD) bit 7-21
Mode Select A (
MODA ) 2-9
Mode Select B ( MODB ) 2-9
Mode Select C ( MODC ) 2-9
Mode Select D ( MODD ) 2-9
modulo adder 1-7
MOVE instruction 6-42
MOVEP instruction 6-22
Multidrop mode 8-2
Multiplication Factor (MF) bits 4-21
Multiplier-Accumulator (MAC) 1-6
, 1-7
N
Negative (N) bit 4-11
Network mode 7-8
Non-Maskable Interrupt (
NMI ) 2-9
O
off-chip memory 1-5 , 3-1
offset adder 1-7
on-chip DRAM controller 1-5
On-Chip Emulation (OnCE) module 1-5
, 1-9
interface 2-29
on-chip memory 1-5 , 1-10
On-Demand mode 7-10 , 7-15
operating mode definitions 4-3
Operating Mode Register (OMR) 1-8
, 4-6 , 4-12 , 6-72
Address Attribute Priority Disable (APD) 4-13
Address Trace Enable (ATE) 4-13
Asynchronous Bus Arbitration Enable (ABE) 4-13
Bus Release Timing (BRT) 4-14
Cache Burst Mode Enable (BE) 4-14
Chip Operating Mode (MD–MA) 4-15
COM byte 4-12
Core-DMA Priority (CDP) 4-14
EOM byte 4-12
External Bus Disable (EBD) 4-15
Memory Switch Mode (MS) 4-14
programming sheet B-14
SCS byte 4-12
Stack Extension Enable (SEN) 4-12
Stack Extension Overflow Flag (EOV) 4-13
Stack Extension Underflow Flag (EUN) 4-13
Stack Extension Wrap Flag (WRP) 4-12
Stack Extension XY Select (XYS) 4-13
Stop Delay Mode (SD) 4-15
TA Synchronize Select (TAS) 4-14
operating modes 4-2
HI32 6-12
Overflow (V) bit 4-11
Overrun Error Flag (OR) bit 8-18
P
Parity Error (PE) bit 8-17
Parity Error Interrupt Enable (PEIE) 6-29
Parity Error Response (PERR) bit 6-66
PCI Address Parity Error (APER) bit 6-40
PCI bus command 6-45
PCI Bus Command (C[3–0]) bits 6-34
PCI Bus Master Enable (BM) bit 6-66
PCI Byte Enables (BE[3–0]) bits 6-33
PCI Data Burst Length (BL[5–0]) bits 6-32
PCI Data Parity Error (DPER) 6-40
PCI Device Base Class (BC[7–0]) 6-67
PCI Device Program Interface (P[17–10]) 6-67
PCI Device Sub-Class (SC[7–0]) bits 6-67
PCI Host Data Transfer Complete (HDTC) bit 6-39
PCI host-to-DSP data transfers 6-45
PCI idle state 6-13
PCI master
active 6-13
PCI Master Abort (MAB) 6-40
PCI Master Address Request (MARQ) bit 6-40
PCI Master Receive Data Request (MRRQ) bit 6-41
PCI Master Transmit Data Request (MTRQ) 6-41
PCI Master Wait States (MWS) bit 6-41
PCI Memory Address Space 6-47
PCI Memory Space Enable (MSE) 6-66
PCI Mode 6-63
PCI mode 6-13
, 6-45 , 6-63 , 6-64
memory space transactions 6-57
PCI Target Abort (TAB) 6-40
PCI Target Disconnect (TDIS) bit 6-40
PCI Target Retry (TRTY) bit 6-39
PCI Time Out Termination (TO) bit 6-39