Motorola DSP56301 - Manual (Page 38)

External Memory Expansion Port (Port A)
2 -8 DSP56301 User’s Manual
BG Input Ignored Input Bus Grant—Asserted/deasserted synchronous to CLKOUT for proper operation,
BG is asserted by an external bus arbitration circuit when the DSP56301
becomes the next bus master. When BG is asserted, the DSP56301 must wait
until BB is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
The default operation of this bit requires a setup and hold time as specified in
DSP56301 Technical Data (the data sheet). An alternate mode can be invoked:
set the asynchronous bus arbitration enable (ABE) bit (Bit 13) in the OMR. When
this bit is set, BG and BB are synchronized internally. This eliminates the
respective setup and hold time requirements but adds a required delay between
the deassertion of an initial BG input and the assertion of a subsequent BG input.
Note: For operations that do not use the BG bus control function, pull this pin low.
BB Input/
Output Input Bus Busy—Asserted and deasserted synchronous to CLKOUT, BB indicates that
the bus is active. Only after BB is deasserted can the pending bus master
become the bus master (and then assert the signal again). The bus master can
keep BB asserted after ceasing bus activity regardless of whether BR is asserted
or deasserted. Such “bus parking” allows the current bus master to reuse the bus
without rearbitration until another device requires the bus. BB is deasserted by an
“active pull-up” method (that is, BB is driven high and then released and held high
by an external pull-up resistor).
The default operation of this bit requires a setup and hold time as specified in the
DSP56301 Technical Data sheet. An alternate mode can be invoked: set the ABE
bit (Bit 13) in the OMR. When this bit is set, BG and BB are synchronized
internally. See BG for additional information.
Note: BB requires an external pull-up resistor.
BL Output Never
tri-stated;
deasserted Bus Lock— Asserted at the start of an external indivisible Read-Modify-Write
(RMW) bus cycle and deasserted at the end of the write bus cycle. BL remains
asserted between the read and write bus cycles of the RMW bus sequence. BL
can be used to “resource lock” an external multi-port memory for secure
semaphore updates. The only instructions that automatically assert BL are BSET,
BCLR, or BCHG, which accesses external memory. BL can also be asserted by
setting the BLH bit in the BCR register.
CAS Output Tri-stated Column Address Strobe—When the DSP is the bus master, DRAM uses CAS
to strobe the column address. Otherwise, if the bus mastership enable (BME) bit
in the DRAM control register is cleared, the signal is tri-stated.
BCLK Output Tri-stated Bus Clock—When the DSP is the bus master, BCLK is active as a sampling
signal when the program address tracing mode is enabled (that is, the ATE bit in
the OMR is set). When BCLK is active and synchronized to CLKOUT by the
internal PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle. The BCLK
rising edge can be used to sample the internal program memory access on the
A[0–23] address lines.
BCLK Output Tri-stated Bus Clock Not—When the DSP is the bus master, BCLK is the inverse of the
BCLK signal. Otherwise, the signal is tri-stated.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During
Reset
Signal Description