Motorola DSP56301 - Manual (Page 357)

Index
DSP56301 User’s Manual Index -1
A
adder
modulo 1-7
offset 1-7
reverse-carry 1-7
Address Arithmetic Logic Unit (Address ALU) 1-7
Address Attribute 0–3 (
AA[0–3] ) 2-6
Address Attribute Priority Disable (APD) bit 4-13
Address Attribute Registers (AAR) 4-22
, 4-27
Bus Access Type (BAT) 4-29
Bus Address Attribute Polarity (BAAP) 4-28
Bus Address to Compare (BAC) 4-27
Bus Number of Address Bits to Compare (BNC) 4-27
Bus Packing Enable (BPAC) 4-28
Bus Program Memory Enable (BPEN) 4-28
Bus X Data Memory Enable (BXEN) 4-28
Bus Y Data Memory Enable (BYEN) 4-28
programming sheet B-20
address bus
external 2-6
signals 2-1
, 2-6
Address Generation Unit (AGU) 1-7
Address Mode Wakeup 8-3
Address Trace Enable (ATE) bit 4-13
Address Trace mode 1-5
addressing modes 1-4
, 1-8
Alignment Control (ALC) bit 7-16
Arithmetic Saturation Mode (SM) bit 4-7
Asynchronous Bus Arbitration Enable (ABE) bit 4-13
asynchronous data transfer 8-2
Asynchronous mode 7-10
, 8-2 , 8-15 , 8-17 , 8-18
Asynchronous Multidrop mode 8-17
B
barrel shifter 1-4 , 1-6
baud rate generator 1-6
bit-oriented instructions 5-2
bootstrap 3-1
, 3-3
code 8-8
program 4-5
program options, invoking 4-6
ROM 1-5
Boundary Scan Register (BSR) 4-35
Burst Mode Enable (BE) bit 4-14
bursts 6-4
bus
address signals 2-1
data signals 2-1
, 2-6
external address 2-6
external data 2-6
internal 1-10
Bus Access Type (BAT) bits 4-29
Bus Address Attribute Polarity (BAAP) bit 4-28
Bus Address to Compare (BAC) bits 4-27
Bus Area 0 Wait State Control (BA0W) bits 4-24
Bus Area 1 Wait State Control (BA1W) bits 4-23
Bus Area 2 Wait State Control (BA2W) bits 4-23
Bus Area 3 Wait State Control (BA3W) bits 4-23
Bus Busy (
BB ) 2-8
Bus Clock ( BCLK) 2-8
Bus Clock Not ( BCLK ) 2-8
Bus Column In-Page Wait State (BCW) bit 4-26
Bus Control Register (BCR) 4-22
Bit Definitions 4-22
Bus Area 0 Wait State Control (BA0W) 4-24
Bus Area 1 Wait State Control (BA1W) 4-23
Bus Area 2 Wait State Control (BA2W) 4-23
Bus Area 3 Wait State Control (BA3W) 4-23
Bus Default Area Wait State Control (BDFW) 4-23
Bus Lock Hold (BLH) bit 4-22
Bus Request Hold (BRH) 4-22
Bus Request Hold (BRH) bit 4-22
Bus State (BBS) bit 4-22
programming sheet B-18
bus control signals 2-1
Bus Default Area Wait State Control (BDFW) bits 4-23
Bus DRAM Page Size (BPS) bit 4-26
Bus Grant (
BG ) 2-8
Bus Interface Unit (BIU)
Address Attribute Registers (AAR) 4-22
Bus Control Register (BCR) 4-22
DRAM Control Register (DCR) 4-22
Bus Lock ( BL ) 2-8
Bus Mastership Enable (BME) bit 4-25
Bus Number of Address Bits to Compare (BNC) bits 4-27
Bus Packing Enable (BPAC) bit 4-28
Bus Page Logic Enable (BPLE) bit 4-26
Bus Program Memory Enable (BPEN) bit 4-28
Bus Refresh Enable (BREN) bit 4-25
Bus Refresh Prescaler (BRP) bit 4-25
Bus Refresh Rate (BRF) bit 4-25
Bus Release Timing (BRT) bit 4-14
Bus Request (
BR ) 2-7
Bus Request Hold (BRH) bit 4-22