Motorola DSP56301 - Manual (Page 358)

Index -2 DSP56301 User’s Manual
Bus Row Out-of-Page Wait States (BRW) bit 4-26
Bus Software Triggered Reset (BSTR) bit 4-25
Bus Strobe (
BS ) 2-7
Bus X Data Memory Enable (BXEN) bit 4-28
Bus Y Data Memory Enable (BYEN) bit 4-28
C
Cache Burst Mode Enable (BE) bit 4-14
Cache Enable (CE) bit 3-7
, 4-7 , 4-8
Cache Line Size (CLS[7–0]) bits 6-69
Cache Line Size Configuraiton Register (CCLS) 6-34
Carry (C) bit 4-11
Central Processing Unit (CPU) 1-1
Chip Operating Mode (MD–MA) bits 4-15
Class Code/Revision ID Configuration Register
(CCCR/CRID) 6-67
PCI Device Base Class (BC[7–0]) 6-67
PCI Device Program Interface (P[17–10]) 6-67
PCI Device Sub-Class (SC[7–0]) 6-67
Revision ID (RID[7–0]) 6-67
Clear Transmitter (CLRT) bit 6-29
clock 2-1
, 2-5
signals 2-5
Clock Divider (CD) bits 8-20
clock generator 7-11
, 7-17
Clock Generator (CLKGEN) 1-9
Clock Out Divider (COD) 8-19
Clock Output (
CLKOUT ) 2-5
Clock Output Disable (COD) bit 4-21
Clock Polarity (CKP) bit 7-22
Clock Prescaler (SCP) 8-19
Clock Source Direction (SCKD) bit 7-22
CMOS design 1-6
code compatibility 1-4
codec 7-4
, 7-10 , 7-13
Column Address Strobe ( CAS ) 2-8
COM byte 4-12
Condition Code Register (CCR) 4-7
Carry (C) 4-11
Extension (E) 4-11
Limit (L) 4-11
Negative (N) 4-11
Overflow (V) 4-11
Scaling (S) 4-10
Unnormalized (U) 4-11
Zero (Z) 4-11
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-32
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Direction (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-33
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable (RLIE) 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Directions (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable (TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
control register mapping 5-2
conventions,document 1-2
core
Data ALU 1-4
Program Control Unit (PCU) 1-4
Core Priority (CP) bits 4-7
Core-DMA Priority (CDP) bits 4-14
Crystal (
XTAL ) output 2-5
crystal frequency 8-6
Crystal Range (XTLR) bit 4-21
D
data alignment, input 6-3
Data Arithmetic Logic Unit (Data ALU) 1-4
, 1-6 , 1-7
registers 1-7
data bus
external 2-6
signals 2-1
, 2-6
Data Input (DI) bit 9-29
data memory expansion 1-5
Data Output (DO) bit 9-29
Data Parity Reported (DPR) bit 6-65
Data Transfer Format Control (FC[1–0]) bits 6-31
data transfer format converter 6-63
data transfer methods 5-2
deadlock, HI32 6-46
Debug Event (
DE 2-29