Motorola DSP56301 - Manual (Page 180)

Host-Side Programming Model
6 -62 DSP56301 User’s Manual
the pins and their alignment. (See Section 6.3.2, DSP-To-Host Data Path, on page 6-7 and
Section 6.3.1, Host-to-DSP Data Path, on page 6-6).
In a PCI mode (DCTR[HM] = $1) memory space read transaction, the HRXS is accessed if
the PCI address is between HI32_base_address: $01C and HI32_base_address: $FFFC. The
host processor views HRXS as a 16377 Dword read-only memory. In PCI DSP-to-host data
transfers via the HRXS, all four byte lanes are driven with data, in accordance with HRF[1–0]
bits, regardless of the value of the byte enable pins (
HC3 / HBE3 - HC0 / HBE0 ).
In a Universal Bus mode (DCTR[HM] = $2 or $3), the HRXS is accessed if the HA[10–3]
value matches the HI32 base address (CBMA, see Section 6.8.11, Memory Space Base
Address Configuration Register (CBMA), on page 6-70) and the
HA[2–0] value is $7. In a
24-bit data Universal Bus mode (DCTR[HM] = $2 or $3 and HCTR[HRF] = $0), the HRXS is
viewed by the host processor as a 24-bit read-only register.
HD[23–0] pins are driven with all
three bytes of the HRXS in a read access. In a 16-bit data Universal Bus mode (DCTR[HM] =
$2 or $3 and HCTR[HRF]
≠
$0), the HRXS is viewed by the host processor as a 16-bit
read-only register. In a read access, the HD[15–0] pins are driven with data from the two most
significant bytes or two least significant bytes of the HRXS, as defined by the HCTR[HRF]
bits. When HSTR[HRRQ] is set and HCTR[RREQ] is set:
n The HREQ status bit is set in the HSTR.
n The HIRQ pin is asserted, if DMAE is cleared (in the Universal Bus modes).
n The HDRQ pin is asserted, if DMAE is set (in the Universal Bus modes).
If TWSD is cleared, the HI32, as the selected PCI target (DCTR[HM] = $1) in a read data
phase from the HRXS inserts PCI wait states if the HRXS is empty (HRRQ = 0). Wait states
are inserted until the data is transferred from the DSP side to the HRXS. Up to eight wait
states can be inserted before a target-initiated transaction termination (disconnect-C/Retry) is
generated.
In a Universal Bus mode read from the HRXS, the HI32 inserts wait states if the HRXS is
empty (HRRQ = 0). Wait states are inserted until the data transfers from the DSP side to the
HRXS. Hardware, software and personal software resets empty the HRXS (HSTR[HRRQ] is
cleared).
6.8.6 Host Transmit Data Register (HTXR)
The HTXR is the input stage of the host-to-DSP data path FIFO for host-to-DSP data
transfers. The DSP56300 core cannot access HTXR. The host processor can write to the
HTXR if the HSTR[HTRQ] bit is set. Data should not be written to the HTXR until
HSTR[HTRQ] is set to prevent previous data from being overwritten. Filling the HTXR by
host processor writes clears HSTR[HTRQ].