7 essi transmit data registers (tx[2–0]), 8 essi time slot register (tsr), 9 transmit slot mask registers (tsma, tsmb) – Motorola DSP56301 User Manual
Page 231: Essi transmit data registers (tx[2–0]) -33, Essi time slot register (tsr) -33, Transmit slot mask registers (tsma, tsmb) -33, Essi transmit slot mask register a (tsma) -33, 7 essi transmit data registers (tx[2–0]), 8 essi time slot register (tsr), 9 transmit slot mask registers (tsma, tsmb)
ESSI Programming Model
Enhanced Synchronous Serial Interface (ESSI)
7
-33
7.5.7
ESSI Transmit Data Registers (TX[2–0])
ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01
TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers
automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The
data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When
the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit
data register empty interrupt has been enabled, the DSP is interrupted whenever a transmit
data register becomes empty.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
while any status bits affected by this operation are updated. If any of those status
bits are read during the two-cycle delay, the status bit may not reflect the current
status.
7.5.8
ESSI Time Slot Register (TSR)
TSR is effectively a write-only null data register that prevents data transmission in the current
transmit time slot. For timing purposes, TSR is a write-only register that behaves as an
alternative transmit data register, except that, rather than transmitting data, the transmit data
signals of all the enabled transmitters are in the high-impedance state for the current time slot.
7.5.9
Transmit Slot Mask Registers (TSMA, TSMB)
Both transmit slot mask registers are read/write registers. When the TSMA or TSMB is read
to the internal data bus, the register contents occupy the two low-order bytes of the data bus,
and the high-order byte is filled by 0. In Network mode the transmitter(s) use these registers
to determine which action to take in the current transmission slot. Depending on the bit
settings, the transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data
word and generate a transmitter empty condition.
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
11
10
9
8
7
6
5
4
3
2
1
0
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)
Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA)