Motorola DSP56301 - Manual (Page 23)

DSP56300 Core Functional Blocks
Overview 1 -7
1.4.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
24-bit operands. The source operands for the data ALU can be 24, 48, or 56 bits in 24-bit
mode or 16, 32, or 40 bits in 16-bit mode. They always originate from data ALU registers.
The results of all data ALU operations are stored in an accumulator. Data ALU operations are
performed in two clock cycles in a pipeline so that a new instruction can be initiated in every
clock cycle, yielding an effective execution rate of one instruction per clock cycle.
1.4.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts
as many as three input operands and outputs one 56-bit result of the following form:
extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit
×
24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be
stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is
performed if specified.
1.4.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU
has four sets of register triplets, and each register triplet includes an address register, offset
register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A
second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in
parallel and share common inputs. The only difference between them is that the carry
operation propagates in opposite directions. Test logic determines which of the three summed
results of the full adders is output.
Each address ALU can update one address register from its own address register file during
one instruction cycle. The contents of the associated modifier register specify the type of