Motorola DSP56301 - Manual (Page 211)

Operating Modes: Normal, Network, and On-Demand
Enhanced Synchronous Serial Interface (ESSI) 7 -13
7.4.8 Byte Format (LSB/MSB) for the Transmitter
Some devices, such as CODECs, require a MSB-first data format. Other devices, such as
those that use the AES–EBU digital audio format, require the LSB first. To be compatible
with all formats, the shift registers in the ESSI are bidirectional. You select either MSB or
LSB by programming CRB[SHFD].
n If CRB[SHFD] is cleared, data is shifted into the receive shift register MSB first and
shifted out of the transmit shift register MSB first.
n If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and shifted
out of the transmit shift register LSB first.
7.4.9 Flags
Two ESSI signals (SC[1–0]) are available for use as serial I/O flags. Their operation is
controlled by the SYN, SCD[1–0], SSC1, and TE[2–1] bits in the CRB/CRA.The control bits
OF[1–0] and status bits IF[1–0] are double-buffered to and from SC[1–0]. Double-buffering
the flags keeps the flags in sync with TX and RX.
The SC[1–0] flags are available in Synchronous mode only. Each flag can be separately
programmed. The
SC0 flag is enabled when transmitter 1 is disabled (TE1 = 0). The flag’s
direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When
SCD0 is cleared, SC0 is configured as input. Similarly, the SC1 flag is enabled when
transmitter 2 is disabled (TE2 = 0), and the SC1 signal is not configured as the transmitter 0
drive-enabled signal (Bit SSC1 = 0). The direction of SC1 is determined by the SCD1 bit.
When SCD1 is set, SC1 is an output flag. When SCD1 is cleared, SC1 is an input flag.
When programmed as input flags, the value of the SC[1–0] bits is latched at the same time as
the first bit of the received data word is sampled. Once the input is latched, the signal on the
input flag signal (
SC0 and SC1 ) can change without affecting the input flag. The value of
SC[1–0] does not change until the first bit of the next data word is received. When the
received data word is latched by RX, the latched values of SC[1–0] are latched by the SSISR
IF[1–0] bits, respectively, and can be read by software.
When they are programmed as output flags, the value of the SC[1–0] bits is taken from the
value of the OF[1–0] bits. The value of OF[1–0] is latched when the contents of TX transfer
to the transmit shift register. The value on SC[1–0] is stable from the time the first bit of the
transmit data word transmits until the first bit of the next transmit data word transmits.
Software can directly set the OF[1–0] values, allowing the DSP56301 to control data
transmission by indirectly controlling the value of the SC[1–0] flags.