Contents
v
Chapter
1
Overview
1.1
Manual Organization ............................................................................................................. 1-1
1.2
Manual Conventions .............................................................................................................. 1-2
1.3
DSP56300 Core Features....................................................................................................... 1-4
1.4
DSP56300 Core Functional Blocks ....................................................................................... 1-6
1.4.1
Data ALU............................................................................................................................... 1-6
1.4.1.1
Data ALU Registers......................................................................................................... 1-7
1.4.1.2
Multiplier-Accumulator (MAC) ...................................................................................... 1-7
1.4.2
Address Generation Unit (AGU) ........................................................................................... 1-7
1.4.3
Program Control Unit (PCU) ................................................................................................. 1-8
1.4.4
PLL and Clock Oscillator ...................................................................................................... 1-9
1.4.5
JTAG TAP and OnCE Module .............................................................................................. 1-9
1.4.6
On-Chip Memory................................................................................................................. 1-10
1.5
Internal Buses ...................................................................................................................... 1-10
1.6
DMA .................................................................................................................................... 1-11
1.7
Peripherals ........................................................................................................................... 1-12
1.7.1
General-Purpose Input/Output (GPIO) signals.................................................................... 1-12
1.7.2
Host Interface (HI32)........................................................................................................... 1-12
1.7.3
Enhance Synchronous Serial Interface (ESSI) .................................................................... 1-12
1.7.4
Serial Communications Interface (SCI)............................................................................... 1-13
1.7.5
Triple Timer Module ........................................................................................................... 1-13
1.8
Related Documents and Web Sites ...................................................................................... 1-14
2
Signals/Connections
2.1
Power ..................................................................................................................................... 2-4
2.2
Ground ................................................................................................................................... 2-4
2.3
Clock ...................................................................................................................................... 2-5
2.4
PLL ........................................................................................................................................ 2-5
2.5
External Memory Expansion Port (Port A) ........................................................................... 2-6
2.5.1
External Address Bus............................................................................................................. 2-6
2.5.2
External Data Bus .................................................................................................................. 2-6
2.5.3
External Bus Control ............................................................................................................. 2-6
2.6
Interrupt and Mode Control ................................................................................................... 2-9
2.7
Host Interface (HI32)........................................................................................................... 2-10
