Motorola DSP56301 - Manual (Page 204)

Operation
7 -6 DSP56301 User’s Manual
7.2.6 Serial Control Signal (SC2)
ESSI0:SC02; ESSI1:SC12
SC2 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode and
for the transmitter only in Asynchronous mode. The direction of this signal is determined by
the SCD2 bit in the CRB. When configured as an output, this signal outputs the internally
generated frame sync signal. When configured as an input, this signal receives an external
frame sync signal for the transmitter in Asynchronous mode and for both the transmitter and
receiver when in Synchronous mode.
SC2 can be programmed as a GPIO signal ( P2 ) when the
ESSI SC2 function is not in use.
7.3 Operation
This section discusses ESSI basics: reset state, initialization, and exceptions.
7.3.1 ESSI After Reset
A hardware RESET signal or software RESET instruction clears the port control register and
the port direction control register, thus configuring all the ESSI signals as GPIO. The ESSI is
in the reset state while all ESSI signals are programmed as GPIO; it is active only if at least
one of the ESSI I/O signals is programmed as an ESSI signal.
7.3.2 Initialization
To initialize the ESSI, do the following:
1. Send a reset: hardware RESET signal, software RESET instruction, ESSI individual
reset, or STOP instruction reset.
2. Program the ESSI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one signal as ESSI signal.
5. If an external frame sync is used, from the moment the ESSI is activated, at least five
(5) serial clocks are needed before the first external frame sync is supplied. Otherwise,
improper operation may result.
When the PC[5–0] bits in the GPIO Port Control Register (PCR) are cleared during program
execution, the ESSI stops serial activity and enters the individual reset state. All status bits of
the interface are set to their reset state. The contents of CRA and CRB are not affected. The
ESSI individual reset allows a program to reset each interface separately from the other
internal peripherals. During ESSI individual reset, internal DMA accesses to the data registers
of the ESSI are not valid, and data read there are undefined. To ensure proper operation of the