Motorola DSP56301 - Manual (Page 227)

ESSI Programming Model
Enhanced Synchronous Serial Interface (ESSI) 7 -29
7.5.4 ESSI Receive Shift Register
The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives incoming data
from the serial receive data signal. The selected (internal/external) bit clock shifts data in
when the associated frame sync I/O is asserted. Data is received MSB first if SHFD is cleared
and LSB first if SHFD is set. Data transfers to the ESSI Receive Data Register (RX) after 8,
12, 16, 24, or 32 serial clock cycles are counted, depending on the word length control bits in
the CRA.
3 RFS 0 Receive Frame Sync Flag
When set, the RFS bit indicates that a receive frame sync occurred during
the reception of a word in the serial receive data register. In other words,
the data word is from the first time slot in the frame. When the RFS bit is
cleared and a word is received, it indicates (only in Network mode) that the
frame sync did not occur during reception of that word. RFS is valid only if
the receiver is enabled (that is, if the RE bit is set).
Note: In Normal mode, RFS is always read as 1 when data is read
because there is only one time slot per frame, the frame sync
time slot.
2 TFS 0 Transmit Frame Sync Flag
When set, TFS indicates that a transmit frame sync occurred in the current
time slot. TFS is set at the start of the first time slot in the frame and
cleared during all other time slots. If the transmitter is enabled, data
written to a transmit data register during the time slot when TFS is set is
transmitted (in Network mode) during the second time slot in the frame.
TFS is useful in Network mode to identify the start of a frame. TFS is valid
only if at least one transmitter is enabled that is, when TE0, TE1, or TE2 is
set).
Note: In Normal mode, TFS is always read as 1 when data is being
transmitted because there is only one time slot per frame, the
frame sync time slot.
1 IF1 0 Serial Input Flag 1
The ESSI latches any data on the SC1 signal during reception of the first
received bit after the frame sync is detected. IF1 is updated with this data
when the data in the receive shift register transfers into the receive data
register. IF1 is enabled only when SC1 is an input flag and Synchronous
mode is selected; that is, when SC1 is programmed as ESSI in the port
control register (PCR), the SYN bit is set, and the TE2 and SCD1 bits are
cleared. If it is not enabled, IF1 is cleared.
0 IF0 0 Serial Input Flag 0
The ESSI latches any data on the SC0 signal during reception of the first
received bit after the frame sync is detected. The IF0 bit is updated with
this data when the data in the receive shift register transfers into the
receive data register. IF0 is enabled only when SC0 is an input flag and
the Synchronous mode is selected; that is, when SC0 is programmed as
ESSI in the port control register (PCR), the SYN bit is set, and the TE1
and SCD0 bits are cleared. If it is not enabled, the IF0 bit is cleared.
Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description