Motorola DSP56301 - Manual (Page 22)

DSP56300 Core Functional Blocks
1 -6 DSP56301 User’s Manual
— Serial Communications Interface (SCI) with baud rate generator
— Triple timer module
— Up to forty-two programmable General Purpose Input/Output (GPIO) pins,
depending on which peripherals are enabled
n Reduced power dissipation
— Very low power CMOS design
— Wait and Stop low-power standby modes
— Fully-static logic
— Optimized power management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.4 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are as follows:
n Data arithmetic logic unit (ALU)
n Address generation unit
n Program control unit
n PLL and clock oscillator
n JTAG TAP and OnCE module
In addition, the DSP56301 provides a set of on-chip peripherals, discussed in Section 1.7,
Peripherals, on page 1-12.
1.4.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
n Fully pipelined 24
×
24-bit parallel multiplier-accumulator
n Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
n Conditional ALU instructions
n Software-controllable 24-bit or 16-bit arithmetic support
n Four 24-bit input general-purpose registers: X1, X0, Y1, and Y0
n Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
n Two data bus shifter/limiter circuits