Rockwell Automation SD3000 Drive Configuration, Programming - Manual (Page 34)

3.3 Command Registers (Registers 100/1 99/1 100-1199)
The Command Registers view is used to configure command registers. These registers are used for
command data sent to the PMI by the UDC module at the end of every scan of the UDC Processor.
Note that the bits in these registers (except bit 15 in register 100/1 100) are used to command action
only and do not indicate the status of the action commanded. The feedback registers (registers
200/1 200 to 299/1 299) are provided for this purpose. The status of the command registers is not
retained after a Stop All.
100/1 100 Drive Control Register
The Drive Control register contains the bits that control the operation of the drive. The SD3000 drive
can operate in one of several modes as shown in Appendix G. The default operating mode is idle;
the other modes are selected in the Drive Control register. (Each of these modes is described in de-
tail in the SD3000 Diagnostics, Troubleshooting, and Start-Up Guidelines instruction manual.)
All bits in this register (except bit 15) can only be written to by a task on an AutoMax Processor; it
cannot be written to by a task on a UDC module. All read/write bits in this register are edge-sensitive
and must be maintained in order to assert the commands.
Bit: 0
Hex Value: 0001
H
Sug. Var. Name: CML_RUN@
Range: N/A
Access: Read/Write
UDC Error Code: N/A
LED: N/A
Description: The Current Minor Loop Run bit is set to request the M-contactor, if present, to close
and to start the drive, i.e., this bit tells the PMI Processor to begin executing the current minor loop.
When this bit is turned off, zero current is commanded until discontinous conduction is detected and
then the M-contactor, if present, is opened. (See register 200/1 200, bit 1). Refer to register 205/1 205
for additional information on the Interlock register.
Bit: 1
Hex Value: 0002H
Sug. Var. Name:
CML_ID@
Range: N/A
Access: Read/Write
UDC Error Code: N/A
LED: N/A
Description: The Enable Armature Identification Test bit is set to start the test in which the resistance
and time constant of the armature are identified. This bit must stay on during the test. Refer to regis-
ter 200/1 200, bit 1 for more information.
Note that if you have performed auto-tuning and the results of the Identification test are consistently
at the tunables’ upper/ lower limits, the local tunable values may be clamped, in which case you may
have to change the CURRENT value. Refer to section 4.2.2 for more information.
Bit: 2
Hex Value: 0004H
Sug. Var. Name:
CML_AT@
Range: N/A
Access: Read/Write
UDC Error Code: N/A
LED: N/S
Description:
The Enable Armature Alpha Test bit is set to start the alpha test of the armature. This bit
only enables the test. The firing angle value is entered into the Armature Test Angle register 102/1 102
(CML ALPHA%). The status of bit 3 defines which bridge is tested, either forward or reverse. To test
the reverse bridge, set bit 3.
RCUIT. UNCONTROLLED MACHINE
FOLLOWED. FAILURE TO OBSERVE
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